Patent Drafting Analysis of Origin Quantum Computing Technology’s Josephson Junction Fabrication Method | US 12,207,568 B2
Patent Drafting Analysis of Origin Quantum's Josephson Junction Fabrication Method | US 12,207,568 B2
A structural and strategic analysis of US 12,207,568 B2 covering claim architecture, drafting quality, critical gaps, and prosecution positioning for Origin Quantum's pre-test-and-transfer Josephson junction fabrication process.
Spec Words
5,200
Across 6 sections
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Total Claims
16
1 independent · 15 dependent
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Figure Sheets
7
Quantum chip structure, fabrication flowchart, process steps
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Published by PatSnap Insights Team · · 12 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 50% of total words (~2,600 of ~5,200), providing substantial process step elaboration across Steps S100–S500, while the claims section (~1,300 words) reflects the density of a single independent claim with 15 dependents layering process sub-steps. The patent contains 16 claims — one broad independent method claim and 15 dependent claims — covering a five-step fabrication process for superconducting circuits integrating Josephson junction pre-testing and physical transfer. Seven drawing sheets across 11 distinct figures (FIG. 1, FIG. 2, FIG. 3A–3E, FIG. 4, FIG. 5, FIG. 6A, FIG. 6B) provide thorough process-step-by-step structural illustration.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 7 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1 | Schematic structural diagram of a quantum chip of a superconducting system in the related art, showing substrate 1, superconducting metal layer 2 with elements 21 and 22, and Josephson junctions 3 arranged in a closed-loop apparatus.Search in Eureka ↗ | Other |
| FIG. 2 | Flowchart of the fabrication method showing the five sequential process steps S100 through S500 as recited in Claim 1, from determining junction regions through forming connection structures.Search in Eureka ↗ | Flow diagram |
| FIG. 3A | Schematic structural diagram corresponding to Step S100, showing substrate 1, superconducting metal layer 2 with first electrical element 21 and second electrical element 22, core region 4, and test region 5 with first conductive plate 23 and second conductive plate 24.Search in Eureka ↗ | Key embodiment |
| FIG. 3B | Schematic structural diagram corresponding to Step S200, illustrating Josephson junction 3 formed in second junction region 51, with first superconducting layer 31 and second superconducting layer 33 electrically connected to conductive plates 23 and 24 via transition structures 71 and 72.Search in Eureka ↗ | Key embodiment |
| FIG. 3C | Schematic structural diagram corresponding to Step S300, showing conductive plates 23 and 24 connected to a detection circuit, with graft structure 6 visible alongside the test region 5 and core region 4 on substrate 1.Search in Eureka ↗ | Claim support |
| FIG. 3D | Schematic structural diagram corresponding to Step S400, showing graft structure 6 after cutting and removal from the second junction region 51, ready for transfer to first junction region 41 on the substrate.Search in Eureka ↗ | Claim support |
| FIG. 3E | Schematic structural diagram corresponding to Step S500, showing first connection structure 81 connecting superconducting layer 31 to first electrical element 21 and second connection structure 82 connecting superconducting layer 33 to second electrical element 22.Search in Eureka ↗ | Key embodiment |
| FIG. 4 | Enlarged schematic diagram of graft structure 6 showing second portion substrate 511, first superconducting layer 31, oxide film layer 32, and second superconducting layer 33, with the three-layer S-I-S stack detail of the Josephson junction.Search in Eureka ↗ | Key embodiment |
| FIG. 5 | Schematic diagram of an alternative connection structure for the electrical connection between Josephson junction 3, first conductive plate 23, and second conductive plate 24, showing parallel-extending first transition structure 71 and second transition structure 72.Search in Eureka ↗ | Other |
| FIG. 6A | Schematic diagram of a partial structure of a first mask pattern layer 9 for forming Josephson junction 3 in second junction region 51, showing junction fabrication window 91 with deposition windows 911, 912 and transition window 92 with windows 921, 922.Search in Eureka ↗ | Claim support |
| FIG. 6B | Schematic diagram of an alternative mask pattern layer 9 structure for forming Josephson junction 3 in second junction region 51, with angled transition windows 921 and 922 enabling directional ion beam etching to remove oxide layers without damaging the junction.Search in Eureka ↗ | Claim support |
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Claims
Claim Architecture Analysis
The patent contains a single independent method claim (Claim 1) with 15 dependent claims — a dependent-to-independent ratio of 15:1, which is markedly above the typical norm for the semiconductor/quantum device fabrication IPC class H10N. All 16 claims are method claims, with no apparatus or system claims filed, leaving the structural product form of the quantum chip unprotected. Claim 1 establishes the core five-step process, while Claims 2–16 layer in sub-step details including patterning processes, junction region geometry, barrier layer composition, cutting technology, and oxide removal steps.
Core inventive concept: Claim 1 solves the low yield problem of quantum chips by decoupling Josephson junction fabrication and testing from its final circuit location — forming the junction first in a pre-wired 'second junction region' with accessible conductive plates, detecting whether its electrical parameter falls 'within a target parameter range,' and only then cutting and transferring the qualified junction to the 'first junction region' between the first and second electrical elements via physical graft transfer, rather than fabricating in-situ under undetectable conditions.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A fabrication method for a superconducting circuit, wherein the superconducting circuit comprises a Josephson junction, and the Josephson junction comprises a first superconducting layer electrically connected to a first electrical element and a second superconducting layer electrically connected to a second electrical element | comprises | determining first junction region and second junction region on substrate; forming Josephson junction in second junction region with S-layer electrical connections to conductive plates; connecting conductive plates to detection circuit to detect electrical parameter within target parameter range; if within range, separating junction via cutting and moving to first junction region; forming first and second connection structures connecting superconducting layers to electrical elementsSearch prior art ↗ |
Claim Dependency Tree
1 Fabrication method for superconducting circuit — five-step process: determine regions, form Josephson junction in test region, detect electrical parameter, cut and transfer qualified junction to circuit region, form connection structuresSearch Claim 1 prior art ↗
2 Adds: first electrical element, second electrical element, first conductive plate, and second conductive plate formed in advance by patterning processSearch in Eureka ↗
3 Adds: second junction region comprises first deposition region and second deposition region with partial overlapSearch in Eureka ↗
4 Adds: barrier layer is formed between the first superconducting layer and the second superconducting layerSearch in Eureka ↗
5 Further: barrier layer is an oxide film layer (depends on Claim 4)Search in Eureka ↗
6 Adds: first electrical element is a capacitor and second electrical element is a ground layerSearch in Eureka ↗
7 Adds: separating step comprises cutting and removing graft structure including second portion substrate and Josephson junction; forming first junction groove; moving graft structure into grooveSearch in Eureka ↗
8 Further: microscopic cutting is performed by focused ion beam; second junction groove synchronously formed after graft removal (depends on Claim 7)Search in Eureka ↗
9 Adds: forming Josephson junction in second junction region via three sub-steps — forming superconducting material layer, oxidizing to form first superconducting layer and oxide film layer, forming second superconducting layer on oxide film layerSearch in Eureka ↗
10 Adds: alternative junction-forming approach — sequentially forming first superconducting layer, oxide film layer, second superconducting layer with partial overlap to form junction; forming first and second transition structures covering respective layers and platesSearch in Eureka ↗
11 Further: extending direction of first transition structure differs from extending direction of first superconducting layer (depends on Claim 10)Search in Eureka ↗
12 Further: extending direction of second transition structure differs from extending direction of second superconducting layer (depends on Claim 10)Search in Eureka ↗
13 Further: extending directions of first and second transition structures are parallel to each other (depends on Claim 10)Search in Eureka ↗
14 Further: before forming transition structures, removing oxide layer on surface of first conductive plate and second conductive plate (depends on Claim 10)Search in Eureka ↗
15 Further: removing oxide layer on conductive plates by ion beam etching (depends on Claim 14)Search in Eureka ↗
16 Adds: before forming connection structures, removing oxide layer on surface of first electrical element and second electrical elementSearch in Eureka ↗
| Metric | This Application | Semiconductor / Quantum Device Norm |
|---|---|---|
| Total claims | 16 | 15 – 25 |
| Independent claim count | 1 | 2 – 5 |
| Dependent : Independent ratio | 15.0 : 1 | 4 – 8 : 1 |
| Method claims present? | Yes — Claim 1 | Common |
| System / apparatus claims? | No | Common |
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Drafting Quality
Drafting Quality Signals
The patent demonstrates strong specification-to-claim mapping with each of the five steps in Claim 1 directly correlated to a dedicated figure (FIG. 3A–3E) and detailed embodiment description, providing robust written description support. However, the entire claim set contains only method claims — the absence of apparatus and system claims for the fabricated superconducting circuit and quantum chip creates a significant enforcement gap that a well-rounded filing would not have left open.
✅
Antecedent Basis
Antecedent basis is generally clean across the 16 claims. Claim 1 introduces 'a first junction region,' 'a second junction region,' 'a first conductive plate,' 'a second conductive plate,' 'a detection circuit,' and all subsequent claims use 'the' references consistently. Claims 2–16 inherit introduced elements from Claim 1 without introducing orphaned 'the' references. One minor concern: Claim 7 introduces 'a second portion substrate' and 'a first junction groove' without prior antecedent in the preamble, but these are adequately supported in the detailed description at the Step S400 sections.
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Spec–Claim Consistency
Specification support for Claim 1 is comprehensive: the five-step structure of Claim 1 maps one-to-one to Steps S100–S500 described in the detailed description, each with a dedicated figure (FIG. 3A through FIG. 3E). The 'target parameter range' limitation of Claim 1's Step S300 is supported by the lock-in amplifier resistance measurement example at page 8. The transition structure sub-steps in Claims 10–13 are supported by FIGS. 5, 6A, and 6B. All independent claim limitations have identifiable paragraph-level support.
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Transition Word Usage
Claim 1 uses 'comprises' as the primary transition, which is strategically appropriate for a method claim in this technology field as it permits additional undisclosed process steps without invalidating coverage. All dependent claims also use 'comprises' or 'further comprises,' maintaining open-ended scope throughout the dependent chain. No 'consisting of' or 'consisting essentially of' language is present, which correctly avoids unnecessary scope limitation in a complex multi-step fabrication process where equivalent process variations should be encompassed.
✅
§112(f) Means-Plus-Function Risk
No 'means for' or 'step for' language appears anywhere in Claims 1–16, and the claims avoid functional claiming constructions that would trigger §112(f) interpretation. Process steps are recited as structural/procedural actions ('forming,' 'connecting,' 'separating,' 'moving') rather than as functional labels. The 'detection circuit' recited in Claim 1 is a structural element with adequate definiteness support in the specification (lock-in amplifier example, page 8), and does not constitute a means-plus-function element under current Federal Circuit interpretation.
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§101 Eligibility Risk
§101 Alice/Mayo risk is minimal for this patent — Claim 1 recites a concrete physical fabrication process involving tangible substrate manipulation, physical cutting (e.g., focused ion beam cutting per Claim 8), oxide film deposition, and physical transfer of a Josephson junction between defined substrate regions. The claims are directed to a manufacturing process for a physical semiconductor device, firmly within the 'process' category of §101 without any abstract idea component. The patent's technology domain (quantum device fabrication) is squarely within patent-eligible subject matter under current USPTO guidance.
⚠️
Dependent Claim Fallback Quality
While the 15 dependent claims provide detailed sub-step coverage, several represent thin fallback positions: Claims 11, 12, and 13 all depend on Claim 10 and add minor geometric orientation details (extending direction relationships of transition structures), creating three narrow claims that largely overlap in scope and could be combined without meaningful coverage loss. In contrast, Claim 7 (graft structure with second portion substrate) and Claim 8 (focused ion beam cutting) add genuinely distinct technical limitations with separate validity footings. Claims 9 and 10 represent two alternative junction formation methods, which is good fallback architecture, but the chain from Claims 10–15 over-sub-divides a single embodiment rather than adding distinct inventive variation.
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Abstract Quality
The abstract accurately identifies the core innovation — pre-fabricating the Josephson junction in a test region, detecting its electrical parameter, and transferring it to the final circuit location — and is reasonably specific. However, the abstract omits the key distinguishing mechanism of the 'second junction region' with pre-formed conductive plates that enable electrical parameter detection before integration, which is the feature that differentiates this invention from prior art in-situ fabrication methods. An examiner reading only the abstract would understand the process sequence but might not identify the pre-wired test region architecture as the novel element, potentially complicating early examination of novelty.
⚠️
Figure Support Quality
Figure support for method step limitations is thorough — each of the five steps of Claim 1 has a dedicated structural diagram (FIG. 3A–3E), FIG. 4 provides enlarged graft structure detail supporting Claims 7–8, and FIGS. 6A–6B support the mask pattern layer process of Claim 10. However, no figures illustrate the completed superconducting quantum chip in its final operational configuration after all five steps, which would support any potential product-by-process or apparatus claims in a continuation filing. FIG. 1 shows only the prior art configuration, not the inventive final structure, leaving the final product form without positive figure support in the inventive disclosure.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
3.5
Prosecution Defensibility
3.8
Spec–Claim Consistency
4.5
Dependent Claim Coverage
3.2
Claim Type Diversity
1.5
Figure Support Quality
4
Key observation: Specification-to-Claim Consistency scores highest (4.5/5.0) because every limitation of Claim 1's five-step process maps directly to a dedicated figure and detailed description paragraph, providing unusually thorough written description support for a fabrication method patent. Claim Type Diversity scores lowest (1.5/5.0) because the entire 16-claim set consists exclusively of method claims — no apparatus claims, system claims, or product-by-process claims were filed — leaving the physical superconducting circuit and quantum chip product entirely unprotected by this patent. Practitioners should note that a continuation filing adding apparatus claims directed to the superconducting circuit produced by this process, leveraging the well-developed specification, would significantly strengthen Origin Quantum's IP position in this technology space.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No apparatus claims on fabricated quantum chip Single independent claim — no validity fallback Yield improvement system and detection apparatus unclaimed
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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