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Patent Drafting Analysis of QUALCOMM’s ANN Multi-Core Resource Allocation | US 12,099,924 B2
Patent Drafting Analysis of QUALCOMM’s ANN Multi-Core Resource Allocation | US 12,099,924 B2
IP Drafting Analysis · US 12,099,924 B2
Patent Drafting Analysis of QUALCOMM's ANN Multi-Core Resource Allocation | US 12,099,924 B2
A structural and strategic analysis of US 12,099,924 B2, examining claim architecture, drafting quality signals, critical gaps, and prosecution positioning for QUALCOMM's reward-based deep learning workload scheduler.
US 12,099,924 B2Filed: Oct 2, 2020Granted: Sep 24, 2024G06N 3/08G06F 9/50
Published byPatSnap Insights Team · · 10 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 65% of estimated total words (~3,900 of ~5,800), providing substantial technical grounding for the reward-quantification and core-allocation mechanisms. The claim set is compact at 15 claims total — 3 independent (method, apparatus/processor, apparatus/means) and 12 dependent — with figures spread across 7 drawing sheets covering SoC hardware architecture, neural network topology types, software stack layering, speedup graphs, and the three-step method flow. Figure coverage is functional but sparse relative to claim scope, with FIG. 5 and FIG. 6 bearing the majority of direct claim support.
Fully connected neural network 202 illustrating all-to-all neuron connectivity between input and output layers.Search in Eureka ↗
Other
FIG. 2B
Locally connected neural network 204 showing limited connectivity pattern with receptive fields 210, 212, 214, and input 216.Search in Eureka ↗
Other
FIG. 2C
Convolutional neural network 206 illustrating shared-weight convolutional layer 208 applied across an input image.Search in Eureka ↗
Other
FIG. 2D
Deep convolutional network (DCN) 200 showing camera 230 input, feature extraction with convolutional layers 232, feature maps 218/220, first and second feature vectors 224/228, and classification output 222.Search in Eureka ↗
Key embodiment
FIG. 3
Deep convolutional network 350 block diagram showing convolution blocks 354A/354B each containing CONV 356, LNorm 358, and MAX POOL 360 layers, followed by fully connected layers FC1/FC2 362, logistic regression 364, and classification score 366.Search in Eureka ↗
Key embodiment
FIG. 4
Software architecture 400 showing AI application 402, AI function API 406, runtime framework 408 in user space 404, Linux kernel 412 with drivers 414/416/418 in OS space 410, and CPU 422, DSP 424, GPU 426, NPU 428 hardware layer 420.Search in Eureka ↗
System architecture
FIG. 5
Speedup graph 500 plotting execution speedup versus number of processing cores for three ANN tasks — curves 502, 504, 506 — illustrating diminishing returns and differential reward values used to guide core allocation.Search in Eureka ↗
Claim support
FIG. 6
Method flow diagram 600 for operating an ANN showing three sequential steps: quantify reward 602, allocate processing cores based on reward 604, and execute ANN tasks according to core allocation 606.Search in Eureka ↗
Flow diagram
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Claims
Claim Architecture Analysis
The patent contains 3 independent claims: Claim 1 (method), Claim 6 (apparatus/processor-based), and Claim 11 (apparatus/means-plus-function), providing tripartite coverage across enforcement formats. The dependent:independent ratio of 4:1 is below the software/AI industry norm of 5–8:1, indicating relatively thin fallback coverage. Claims 2–5 depend from Claim 1, Claims 7–10 depend from Claim 6, and Claims 12–15 mirror the same dependent structure from Claim 11, creating a parallel but structurally redundant tripartite tree.
Core inventive concept: The claims address the problem of inefficient resource allocation when executing concurrent partial deep learning workloads across multi-core processors by quantifying a reward — defined explicitly in Claims 1, 6, and 11 as "a rate of change in speedup of execution time of each of the ANN tasks over a change in resources" — and allocating processing cores to each task in descending order of that reward value to maximize throughput per allocated resource unit.
Independent Claim Dissection
Claim
Preamble
Transition
Key Body Elements
Claim 1
A processor-implemented method for operating an artificial neural network (ANN)
comprising
quantifying a reward for executing ANN tasks in a multi-core system where reward = rate of change of speedup over change in resources; allocating a set of processing cores to each ANN task based on the reward; executing operations using the allocated processing coresSearch prior art ↗
Claim 6
An apparatus for operating an artificial neural network (ANN)
comprising
at least one memory; at least one processor coupled to the memory configured to: quantify reward (rate of change of speedup over change in resources), allocate processing cores per ANN task based on reward, execute operations using allocated coresSearch prior art ↗
Claim 11
An apparatus for operating an artificial neural network (ANN)
comprising
means for quantifying a reward (rate of change of speedup over change in resources); means for allocating a set of processing cores to execute each ANN task based on the reward; means for executing operations using the allocated coresSearch prior art ↗
Claim Dependency Tree
1 Method: quantify reward (rate-of-change of speedup/resources), allocate cores per ANN task, execute concurrentlySearch Claim 1 prior art ↗
2 Adds: cores for each ANN task allocated in descending order of corresponding rewardSearch in Eureka ↗
3 Adds: each ANN task includes a partial workload having a set of dependent operationsSearch in Eureka ↗
4 Adds: determining speedup values (reduction in execution time above baseline for unit core increases) and reward function via curve fittingSearch in Eureka ↗
6 Apparatus (processor-based): at least one memory + processor configured to quantify reward, allocate cores, execute ANN tasksSearch Claim 6 prior art ↗
7 Adds: processor allocates cores in descending order of corresponding reward per ANN taskSearch in Eureka ↗
8 Adds: each ANN task includes a partial workload having a set of dependent operationsSearch in Eureka ↗
9 Adds: processor further determines speedup values above baseline per unit core increase and reward function via curve fittingSearch in Eureka ↗
11 Apparatus (means-plus-function): means for quantifying reward, means for allocating cores, means for executing ANN tasksSearch Claim 11 prior art ↗
12 Adds: means for allocating cores in descending order of corresponding rewardSearch in Eureka ↗
13 Adds: each ANN task includes a partial workload having a set of dependent operationsSearch in Eureka ↗
14 Adds: means for determining speedup values above baseline per unit core increase and means for determining reward function via curve fittingSearch in Eureka ↗
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Drafting Quality
Drafting Quality Signals
The patent demonstrates strong definitional precision in the reward construct — Claims 1, 6, and 11 all explicitly define reward as a rate-of-change metric — which provides a robust §112(a) written description anchor in FIG. 5 and the accompanying mathematical equations. However, the near-identical parallelism between dependent claims 2–5, 7–10, and 12–15 reveals a structural redundancy that creates limited genuine fallback coverage and exposes the patent to a compactness challenge during reexamination.
✅
Antecedent Basis
Antecedent basis is clean throughout the claim set. In Claim 1, "a reward" is introduced in the quantifying step and correctly referred back as "the reward" in the allocating step; "a set of processing cores" is introduced and re-referenced as "the set of processing cores" in the executing step. The same pattern is consistently applied across parallel Claims 6 and 11, with no orphaned "the" references detected.
The core claim limitations map clearly to specific specification sections. FIG. 5 and Equations (1) and (2) directly support the reward-as-rate-of-speedup-change definition in Claims 1, 6, and 11. FIG. 6 (blocks 602, 604, 606) maps to the three-step method of Claim 1. The curve-fitting limitation in Claim 4 is supported by the detailed description at column 10 discussing curve fitting techniques. No claim limitation appears unsupported by the specification.
All independent claims use "comprising" as the transition word, which is the broadest available transition and appropriate for a software/AI method and apparatus claim set where unlisted elements (additional processing steps or hardware components) should not be excluded. Using "consisting of" here would have been a significant strategic error; the "comprising" choice is correct and maximizes claim scope for both the method and apparatus claims.
Claim 11 and its dependents 12–15 are drafted entirely using "means for" language, triggering mandatory §112(f) interpretation and limiting the claim scope to the disclosed structures and their equivalents. The specification at column 12 identifies the corresponding structures as CPU 102, program memory, memory block 118, fully connected layers 362, NPU 428, and routing connection processing unit 216 — this disclosure is adequate but any accused infringer using a different hardware configuration could argue non-equivalence, narrowing practical enforcement reach compared to Claims 1 and 6.
Claims 1, 6, and 11 are directed to a method and apparatus for resource scheduling of ANN workloads — a field where §101 Alice-step-two analysis is actively applied by examiners. The hardware tie-in in Claim 1 is functional rather than structural ("a system having multiple processing cores" is contextual, not a claimed structural element), creating potential exposure at Alice step 2A prong 2. Claim 6 is stronger because it recites "at least one memory" and "at least one processor" as structural limitations, providing a concrete machine anchor that better withstands Mayo/Alice scrutiny.
The 12 dependent claims are divided into three mirror-image groups (2–5, 7–10, 12–15), each adding the same four limitations: descending reward ordering (Claims 2, 7, 12), partial workload definition (Claims 3, 8, 13), curve-fitting determination (Claims 4, 9, 14), and concurrent execution (Claims 5, 10, 15). While parallel structure is defensible, the lack of any unique dependent claim fallback position — such as specific core types (NPU vs. GPU), specific ANN architectures, or specific scheduling policies beyond descending order — means that if Claim 1 is invalidated, the dependents offer minimal added protection beyond claim type diversity.
The abstract states that a reward is quantified, cores are allocated based on the reward, and tasks are executed concurrently — this correctly identifies the method steps but omits the defining technical limitation: that the reward is specifically a "rate of change in speedup of execution time over a change in resources." An examiner reading only the abstract might classify this as a generic scheduling method and fail to identify the specific quantitative reward-function innovation, potentially weakening prior-art search precision during examination.
The key claim limitations have adequate figure support. FIG. 6 directly maps to the three method steps of Claim 1 (blocks 602/604/606). FIG. 5 supports the reward-as-speedup-slope concept and the descending-reward allocation of Claim 2. FIG. 4 supports the multi-processor apparatus structure of Claim 6 by showing CPU 422, DSP 424, GPU 426, and NPU 428 hardware. The curve-fitting limitation of Claim 4 is supported conceptually by FIG. 5 curves 502–506 but lacks a dedicated figure showing the fitting algorithm, which is a minor gap for that specific dependent limitation.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
3.5
Prosecution Defensibility
3.2
Spec–Claim Consistency
4.2
Dependent Claim Coverage
2.5
Claim Type Diversity
3
Figure Support Quality
3.8
Key observation: Spec–Claim Consistency scores highest (4.2/5.0) because FIG. 5's speedup curves and Equations (1) and (2) provide direct, quantitative written-description support for the reward-definition limitation in all three independent claims — a genuine strength that would withstand a §112(a) challenge. Dependent Claim Coverage scores lowest (2.5/5.0) because Claims 2–5, 7–10, and 12–15 are structurally identical mirror groups adding only four limitations across three claim types, leaving no unique technical fallback positions such as heterogeneous core-type selection or dynamic reward recalculation — practitioners should consider a continuation with claims directed to those unclaimed embodiments described in the detailed description.
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
GAP 01 · HIGHEST IMPACT
No computer-readable medium (CRM) claim filed
The claim set includes a method claim (Claim 1) and two apparatus claims (Claims 6 and 11) but omits a non-transitory computer-readable medium claim — a standard tripartite claim type for software-implemented inventions in the G06N/G06F space. This gap allows a competitor to distribute the scheduling algorithm as firmware or a software package on any storage medium without directly operating the method or the apparatus as claimed, creating a direct design-around path. A stronger filing would have included a CRM claim reciting a non-transitory computer-readable medium with program code to quantify the reward, allocate the cores, and execute the ANN tasks, consistent with the CRM embodiment described in the specification at column 1–2.
Claims 1, 6, and 11 define reward solely as "a rate of change in speedup of execution time" over resource change — limiting the scope to throughput-only optimization. The detailed description at column 10 explicitly discusses that allocation may target "speed and efficiency" and that NPU/GPU/DSP selection is also relevant, but no claim captures a multi-dimensional reward that incorporates power consumption, thermal budget, or energy-per-inference metrics alongside speedup. A competitor implementing a reward function that optimizes power-adjusted throughput rather than raw speedup could argue non-infringement. A stronger filing would have broadened the reward definition in at least one independent claim to encompass "a benefit function based on at least one of speedup, power consumption, or resource utilization."
GAP 03 · HIGH IMPACT
No claim on dynamic reward recalculation per allocation step
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No CRM claim in filingReward scope excludes power metricsNo dynamic per-step reward recalculation claim
US 12,099,924 B2 protects a method and apparatus for operating an artificial neural network (ANN) by quantifying a reward — specifically defined as the rate of change in execution time speedup per unit change in processing resources — and using that reward to allocate processing cores of a multi-core system to concurrent ANN tasks in descending reward order. The patent covers the full loop of reward quantification, reward-based core allocation, and concurrent ANN task execution across CPU, GPU, DSP, and NPU processing cores.
US 12,099,924 B2 is assigned to QUALCOMM Incorporated, headquartered in San Diego, California, USA. The sole inventor is Rajeswaran Chockalingapuramravindran, also based in San Diego, California.
Claim 1 is a processor-implemented method comprising: quantifying a reward (rate of change of speedup over resource change), allocating processing cores per ANN task based on the reward, and executing operations using the allocated cores. Claim 6 is a processor-based apparatus claim requiring at least one memory and at least one processor configured to perform the same three operations. Claim 11 is a means-plus-function apparatus claim with means for quantifying the reward, means for allocating cores, and means for executing ANN tasks.
This patent covers a system for making artificial intelligence (AI) chips run faster and more efficiently by deciding how many processor cores to give to each neural network task running at the same time. Instead of dividing computing power equally, the system measures how much speed each task gains from getting extra cores — called the "reward" — and gives more cores to whichever task benefits most per additional core allocated. This approach allows multi-core devices like smartphones and edge-AI chips to handle multiple deep learning tasks concurrently with less wasted computation.
G06N 3/08 (2023.01) — Learning methods for artificial neural networks. G06F 9/50 (2006.01) — Allocation of resources in computer systems (e.g., scheduling of programs or processes).
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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