Patent Drafting Analysis of QUALCOMM’s Power Optimized LLM SoC Architecture | US 2025/0068838 A1

IP Drafting Analysis · US 2025/0068838 A1

Patent Drafting Analysis of QUALCOMM's Power Optimized LLM SoC Architecture | US 2025/0068838 A1

Q: What does US 2025/0068838 A1 protect?

US 2025/0068838 A1 protects a power-optimized SoC architecture for running large language model (LLM)-based applications on consumer hardware. The patent covers an apparatus (Claim 1) and a method (Claim 12) in which an LLM processing block is physically co-located with a memory controller and a DDR PHY memory interface within the same voltage domain, shortening the data path to DDR memory and reducing power consumption by approximately 20% compared to conventional NPU-based SoC architectures. The core mechanism is the integration of the LLM compute logic within the PHY DDR voltage domain rather than deep inside the SoC away from memory.

Q: Who owns patent US 2025/0068838 A1?

US 2025/0068838 A1 is owned by QUALCOMM Incorporated, headquartered in San Diego, California, USA. The inventors are Suyash Ranjan (San Diego, CA, US) and Franck Dahan (San Diego, CA, US).

Q: What are the independent claims of US 2025/0068838 A1?

Claim 1 is an apparatus claim covering an LLM-based ML system-on-chip (SoC) comprising a first LLM processing block, a first memory controller coupled to it, a first PHY memory interface coupled to the LLM processing block through the memory controller, and a memory coupled to the PHY memory interface as a first data channel. Claim 12 is a method claim covering the steps of forming a first LLM processing block, coupling it to a first memory controller, coupling the LLM processing block to a first PHY memory interface through the memory controller, and coupling a memory to the PHY memory interface as a first data channel.

Q: What technology does this patent cover?

Running large AI language models like ChatGPT locally on a smartphone requires fetching enormous amounts of data from memory very quickly, which currently forces the phone's AI chip to run at high power and voltage — causing the phone to overheat within seconds. This patent describes a smarter chip layout in which the AI processing circuitry is placed right next to the memory interface hardware, cutting the distance data has to travel and keeping all of that hardware in a lower-power electrical zone. The result is approximately 20% power savings for AI tasks, allowing a phone to run language model applications for much longer without overheating.

Q: What IPC classifications does this patent use?

G06F 40/20 (2020.01) — Linguistic analysis; Syntactic or semantic analysis. G06F 15/78 (2006.01) — Dataflow computers; Architectures based on data flow models.

A structural and strategic analysis of Qualcomm's LLM-based ML SoC patent, examining claim architecture, drafting quality, critical prosecution gaps, and competitive positioning of the PHY-MC-LLM co-location strategy.

US 2025/0068838 A1Filed: Aug 22, 2023Published: Feb 27, 2025G06F 40/20G06F 15/78

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Spec Words

6,800

Across 6 sections

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Total Claims

2 independent · 20 dependent

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Figure Sheets

SoC architecture, neural networks, LLM-MC-PHY blocks, method flow

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Published by PatSnap Insights Team · June 4, 2026 · 12 min read Verified by PatSnap Eureka Data

Overview

Structural Overview

The detailed description dominates at approximately 56% of total specification words (~3,900 of ~6,800), providing solid but not excessive technical grounding for the PHY-MC-LLM co-location architecture. The claim set comprises 22 claims in two independent claims — Claim 1 (apparatus/SoC) and Claim 12 (method) — with 20 dependent claims building fallback positions across both families. The 8 figure sheets span from high-level SoC block diagrams (FIG. 1, FIG. 3) through neural network conceptuals (FIGS. 2A–2D) to the core LLM-MC-PHY architecture embodiments (FIGS. 4A–4C) and method flow (FIG. 5).

Section Word Distribution

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Figure Inventory — 8 Sheets

Figure	Description	Role
FIG. 1	Block diagram of an SoC architecture (100) showing CPU (102), GPU (104), DSP (106), NPU (130), connectivity (110), multimedia (112), sensors (114), ISPs (116), memory (118), and navigation (120) subsystems.Search in Eureka ↗	System architecture
FIG. 2A	Diagram illustrating a fully connected neural network (202) where every neuron in one layer connects to every neuron in the next layer.Search in Eureka ↗	Other
FIG. 2B	Diagram illustrating a locally connected neural network (204) where neurons connect to only a limited number of neurons in the next layer, showing receptive fields (210, 212, 214, 216).Search in Eureka ↗	Other
FIG. 2C	Diagram illustrating a convolutional neural network (206) with shared connection strengths (208) across neurons in a layer.Search in Eureka ↗	Other
FIG. 2D	Detailed diagram of a deep convolutional network (DCN 200) performing image-based feature extraction (218, 220, 232) and classification (222, 224, 228) from a camera input (226, 230).Search in Eureka ↗	Other
FIG. 3	Block diagram of a machine learning SoC (300) showing multiple NPU engines (310-1 through 310-N) connected via NoC (330), with memory controller (340), DDR (350), CPU (360), SoC power management (370), and external interfaces (380).Search in Eureka ↗	System architecture
FIG. 4A	Block diagram of LLM-based ML-SoC (400) showing four data channels (410-0 through 410-3) to DDR memory (470), with co-located LLM processing blocks (420-0 to 420-3), memory controllers MC0–MC3 (440-0 to 440-3), PHY interfaces (430-0 to 430-3), uNOC components (460-0 to 460-3), intercommunication channels (450-0 to 450-2), and NoCsinterconnect framework (402).Search in Eureka ↗	Key embodiment
FIG. 4B	Alternative LLM-based ML-SoC (480) variant showing uNOC components (460-0 to 460-3) provided as separate components from the memory controllers (440-0 to 440-3), with same LLM blocks, PHY interfaces, and intercommunication channels as FIG. 4A.Search in Eureka ↗	Key embodiment
FIG. 4C	LLM-based ML-SoC (490) block diagram showing a simplified variant with LLM processing blocks (420-0 to 420-3) integrated within memory controllers (440-0 to 440-3) and PHY DDR interfaces (430-0 to 430-3) as thin LLM core additions, without separate uNOC components.Search in Eureka ↗	Key embodiment
FIG. 5	Flow diagram (500) illustrating the method for LLM-based application processing: forming a first LLM processing block (502), coupling to a first memory controller (504), coupling to a first PHY memory interface through the first memory controller (506), and coupling memory as a first data channel (508).Search in Eureka ↗	Flow diagram

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Claims

Claim Architecture Analysis

The claim set contains two independent claims — Claim 1 (apparatus: LLM-based ML SoC) and Claim 12 (method for LLM-based ML SoC processing) — providing dual claim-type coverage across hardware and process dimensions. With 20 dependent claims on 2 independent claims, the dependent-to-independent ratio is 10:1, which is well above the typical semiconductor/SoC norm of 4–8:1, reflecting a strong layered fallback strategy. The parallel structure — Claims 1–11 covering the apparatus and Claims 12–22 mirroring those limitations in method form — provides broad enforcement coverage, though the absence of a computer-readable medium (CRM) claim represents a notable gap for software-oriented design-arounds.

Core inventive concept: The claims address the power and thermal bottleneck of running LLM-based applications on consumer SoCs, where NPU engines must fetch high-bandwidth data across a long path to DDR memory at elevated voltage. The solution, as recited in Claims 1 and 12, is a co-located architecture in which 'a first LLM processing block' is integrated within 'a first physical layer (PHY) memory interface coupled to the first LLM processing block through the first memory controller,' placing the LLM compute logic physically adjacent to the DDR PHY to keep the processing chain within the PHY DDR voltage domain and shorten the data path.

Independent Claim Dissection

Claim	Preamble	Transition	Key Body Elements
Claim 1	A large language model (LLM)-based machine learning (ML) system-on-chip (SoC)	comprising	a first LLM processing block; a first memory controller coupled to the first LLM processing block; a first physical layer (PHY) memory interface coupled to the first LLM processing block through the first memory controller; a memory coupled to the first PHY memory interface as a first data channelSearch prior art ↗
Claim 12	A method for a large language model (LLM)-based machine learning (ML) system-on-chip (SoC)	comprising	forming a first LLM processing block; coupling the first LLM processing block to a first memory controller; coupling the first LLM processing block to a first physical layer (PHY) memory interface through the first memory controller; coupling a memory to the first PHY memory interface as a first data channelSearch prior art ↗

Claim Dependency Tree

1 LLM-based ML SoC comprising first LLM processing block, first memory controller, first PHY memory interface, and memory as first data channelSearch Claim 1 prior art ↗

2 Adds: first PHY memory interface comprises DDR PHY voltage domainSearch in Eureka ↗

3 Adds: memory comprises DDR DRAMSearch in Eureka ↗

4 Adds: data channels each coupled to an instance of the first PHY memory interface incorporating the first memory controller, including first LLM processing blockSearch in Eureka ↗

5 Adds: first LLM processing block in a data channel configured to intercommunicate with first LLM processing blocks across data channelsSearch in Eureka ↗

6 Adds: second memory controller having second LLM processing block; second PHY memory interface incorporating second memory controller including second LLM processing block; memory coupled to second PHY memory interface as second data channelSearch in Eureka ↗

7 Adds: intercommunication channel between first LLM processing block and second LLM processing blockSearch in Eureka ↗

8 Adds: first PHY memory interface comprises analog interface to memorySearch in Eureka ↗

9 Adds: first memory controller including first LLM processing block comprises digital interface to first PHY memory interfaceSearch in Eureka ↗

10 Adds: voltage domain of first memory controller and/or first LLM processing block is different from voltage domain of first PHY memory interfaceSearch in Eureka ↗

11 Adds: micro-network-on-chip (uNOC) coupled to first LLM processing block, first memory controller, and NoC/interconnect frameworkSearch in Eureka ↗

12 Method for LLM-based ML SoC: forming first LLM processing block, coupling to first memory controller, coupling to first PHY memory interface through first memory controller, coupling memory as first data channelSearch Claim 12 prior art ↗

13 Adds: first PHY memory interface comprises DDR PHY voltage domainSearch in Eureka ↗

14 Adds: memory comprises DDR DRAMSearch in Eureka ↗

15 Adds: data channels each coupled to an instance of the first PHY memory interface incorporating first memory controller, including first LLM processing blockSearch in Eureka ↗

16 Adds: intercommunicating between first LLM processing block in a data channel with first LLM processing blocks across data channelsSearch in Eureka ↗

17 Adds: integrating second LLM processing block in second memory controller; incorporating second memory controller including second LLM processing block in second PHY memory interface; coupling second PHY memory interface to memory as second data channelSearch in Eureka ↗

18 Adds: forming intercommunication channel between first LLM processing block and second LLM processing blockSearch in Eureka ↗

19 Adds: first PHY memory interface comprises analog interface to memorySearch in Eureka ↗

20 Adds: first memory controller including first LLM processing block comprises digital interface to first PHY memory interfaceSearch in Eureka ↗

21 Adds: voltage domain of first memory controller and/or first LLM processing block is different from voltage domain of first PHY memory interfaceSearch in Eureka ↗

22 Adds: uNOC coupled to first LLM processing block, first memory controller, and NoC/interconnect frameworkSearch in Eureka ↗

Metric	This Application	Semiconductor / SoC Industry Norm
Total claims	22	15 – 25
Independent claim count	2	2 – 4
Dependent : Independent ratio	10.0 : 1	4 – 8 : 1
Method claims present?	Yes — Claim 12	Common
System / apparatus claims?	Yes — Claim 1	Always

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Drafting Quality

Drafting Quality Signals

The claim set's primary strength lies in its clean parallel apparatus/method structure (Claims 1–11 / 12–22) with an unusually high dependent claim ratio (10:1) that provides layered fallback across voltage domain, memory type, intercommunication, and uNOC dimensions. A material weakness is the absence of a computer-readable medium (CRM) or non-transitory storage claim, which creates a design-around vector for software-defined implementations of the LLM processing architecture, and the independent claims' broad recitation of 'first LLM processing block' without structural definition creates potential §112 indefiniteness exposure.

✅

Antecedent Basis

The antecedent basis is clean throughout the 22-claim set. Claim 1 introduces 'a first LLM processing block,' 'a first memory controller,' 'a first physical layer (PHY) memory interface,' and 'a memory,' all correctly referred back with the definite article in Claims 2–11. Dependent Claims 6 and 7 correctly introduce 'a second memory controller' before referring to 'the second memory controller' in subsequent sub-claims. No orphaned 'the' references were found across either the apparatus or method claim family.

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✅

Spec–Claim Consistency

All four limitations of Claim 1 are directly supported by the specification. FIG. 4A (labeled 400) and paragraphs [0038]–[0046] map to the 'first LLM processing block' (420-0), 'first memory controller' (440-0), 'first PHY memory interface' (430-0), and 'memory coupled as first data channel' (DDR memory 470 via channel 410-0). The voltage domain limitation of Claims 2 and 10 is supported at paragraph [0021], and the uNOC limitation of Claim 11 is supported by FIG. 4A/4B and paragraphs [0039]–[0040]. Support is comprehensive for all independent and most dependent claim limitations.

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✅

Transition Word Usage

Both Claim 1 and Claim 12 use 'comprising,' the broadest open-ended transition, which is strategically appropriate for a hardware architecture claim where additional SoC blocks (CPU, GPU, NPU) will always be present in commercial embodiments. The use of 'comprising' ensures that competitors cannot design around by simply adding elements to a Qualcomm Snapdragon-style SoC. No missed opportunities for 'consisting essentially of' were identified, as the architecture is explicitly open to additional processing blocks per paragraphs [0015]–[0016].

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⚠️

§112(f) Means-Plus-Function Risk

The term 'first LLM processing block' in Claims 1 and 12 presents a latent §112(f) risk despite not using 'means for' language: if an examiner or court construes 'processing block' as a functional label without structural definition, it could trigger means-plus-function treatment, limiting the claim to the specific embodiments in FIGS. 4A–4C. The specification at paragraph [0085] explicitly contemplates 'means-plus-function components with similar numbering' for operations illustrated in the figures, which could inadvertently invite such a construction. A stronger filing would have defined the structural components of the LLM processing block (e.g., compute units, weight buffers, activation logic) in the claim body.

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⚠️

§101 Eligibility Risk

Claims 1 and 12, as apparatus and method claims tied to a physical SoC with named hardware components (PHY memory interface, memory controller, DDR memory), present low Alice/Mayo exposure given their concrete hardware tie-in. However, the method claim (Claim 12) uses 'forming,' 'coupling,' and 'integrating' steps that could be characterized as abstract organizational steps without specific hardware-performance outcomes. The strongest §101 defense rests on Claim 1's apparatus framing as a physical 'system-on-chip' with specific memory controller, PHY interface, and data channel hardware — but the absence of any claim element reciting a specific performance improvement (e.g., power savings quantification) weakens the practical application argument during prosecution.

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✅

Dependent Claim Fallback Quality

The dependent claims add genuinely distinct technical fallback positions across multiple dimensions: Claims 2/13 (DDR PHY voltage domain), Claims 3/14 (DDR DRAM memory type), Claims 4–5/15–16 (multi-channel data path with intercommunication), Claims 6–7/17–18 (second memory controller/LLM block architecture), Claims 8/19 (analog interface), Claims 9/20 (digital interface), Claims 10/21 (cross-voltage-domain operation), and Claims 11/22 (uNOC integration). The voltage domain and interface type claims (8–10, 19–21) are particularly strong fallback positions that would survive examiner rejections targeting the broader independent claims, as these are hardware-specific distinctions not commonly found in prior art SoC architectures.

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⚠️

Abstract Quality

The abstract accurately describes the hardware architecture — first LLM processing block, first memory controller, first PHY memory interface, and first data channel memory — but omits the key inventive contribution: that the LLM processing block, memory controller, and DDR PHY interface are physically co-located within the DDR PHY voltage domain to reduce data path length and power consumption. An examiner reading only the abstract would identify this as a generic SoC memory architecture filing rather than a power-optimization invention for LLM inference workloads. This framing gap may contribute to the examiner classifying it in a broader, more crowded art unit.

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✅

Figure Support Quality

The three key architectural embodiment figures (FIGS. 4A, 4B, 4C) provide strong structural support for all apparatus claim limitations: LLM blocks (420-0 to 420-3), memory controllers (440-0 to 440-3), PHY interfaces (430-0 to 430-3), DDR memory (470), data channels (410-0 to 410-3), intercommunication channels (450-0 to 450-2), uNOC (460-0 to 460-3), and NoC framework (402) are all depicted. FIG. 5 supports the method claim steps of Claim 12. The four neural network figures (FIGS. 2A–2D) provide background context but do not support any independent claim limitation, representing approximately 37% of the figure count devoted to non-essential background — a slight inefficiency that reduces the figures-per-claim-limitation ratio.

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Scorecard

Strategic Intent Scorecard

Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.

Claim Breadth

3.8

Prosecution Defensibility

3.5

Spec–Claim Consistency

4.2

Dependent Claim Coverage

Claim Type Diversity

Figure Support Quality

3.5

Key observation: The highest-scoring dimension is Spec–Claim Consistency (4.2/5.0) — FIG. 4A and paragraphs [0038]–[0046] provide exhaustive structural mapping for every element of Claims 1 and 12, with separate embodiment figures (4A, 4B, 4C) covering each configuration variant claimed in the dependent claims. The lowest-scoring dimension is Claim Type Diversity (3.0/5.0) — the absence of a computer-readable medium (CRM) or non-transitory storage medium claim leaves a complete design-around route for competitors who implement the LLM-PHY architecture through firmware configuration rather than fixed hardware, an especially significant gap given that Qualcomm's SoC architectures are routinely configured via device firmware. Practitioners drafting continuations should prioritize a CRM claim and consider adding a chip-level apparatus claim specifically reciting the power savings outcome (approximately 1.5 W / 20% improvement) recited at paragraph [0043] to strengthen the practical application argument.

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Critical Gaps

3 Critical Gaps in This Claim Set

A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.

GAP 01 · HIGHEST IMPACT

No CRM or Non-Transitory Storage Claim Filed

Neither Claim 1 nor Claim 12, nor any dependent claim, covers a non-transitory computer-readable medium or computer program product encoding instructions that configure an SoC to implement the LLM-PHY-MC co-located architecture, leaving the entire software/firmware implementation space unprotected. This creates a direct design-around opportunity for competitors who configure standard SoC hardware via firmware to achieve the same PHY-MC-LLM proximity without permanently integrating the blocks in silicon. A stronger filing would have included a third independent CRM claim mirroring the method steps of Claim 12 in the form 'a non-transitory computer-readable medium having instructions that, when executed by one or more processors, configure a first LLM processing block...,' consistent with the computer-program product language already in the specification at paragraphs [0089] and [0097].

GAP 02 · HIGH IMPACT

"LLM Processing Block" Lacks Structural Definition in Claims

The term 'first LLM processing block' is used across all 22 claims as the central claim element but is defined nowhere in the claim set with structural limitations — it appears solely as a functional label identifying the block by what it does (process LLM operations) rather than what it is (e.g., comprising a weight buffer, attention computation unit, or token processing engine). This creates a §112 indefiniteness risk if the USPTO examiner applies the reasoning that 'processing block' is an unrecognized term of art in the SoC context, potentially requiring disclaimer of scope to the specific embodiments in FIG. 4A–4C. A stronger filing would have either defined the minimum structural components of an LLM processing block in at least one dependent claim (e.g., 'wherein the first LLM processing block comprises a weight cache and a matrix multiplication unit') or provided an explicit lexicographic definition in the specification rather than relying on general LLM context.

GAP 03 · HIGH IMPACT

Power Savings Outcome Not Claimed as Functional Limitation

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3 Critical Gaps in This Claim Set

See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.

No CRM claim on LLM firmware LLM block structurally undefined in claims Power savings not claimed as limitation

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Frequently asked questions

US 2025/0068838 A1 — key questions answered

What does US 2025/0068838 A1 protect?+

Who owns patent US 2025/0068838 A1?+

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What technology does this patent cover?+

What IPC classifications does this patent use?+

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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.

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Patent Drafting Analysis of QUALCOMM’s Power Optimized LLM SoC Architecture | US 2025/0068838 A1

Patent Drafting Analysis of QUALCOMM's Power Optimized LLM SoC Architecture | US 2025/0068838 A1