Patent Drafting Analysis of Samsung Electronics’ Direct Storage Device and Storage System | US 2024/0176540 A1

IP Drafting Analysis · US 2024/0176540 A1

Patent Drafting Analysis of Samsung Electronics' Direct Storage Device and Storage System | US 2024/0176540 A1

Q: What does US 2024/0176540 A1 protect?

US 2024/0176540 A1 protects a storage device and storage system architecture that enables accelerators (such as GPUs, TPUs, or AI engines) to directly access a storage device without routing data through a system-level buffer memory, solving the performance bottleneck caused by indirect access paths in AI and high-performance computing workloads. The mechanism uses one or more physical functions exposed through one or more ports of the storage device, combined with a first buffer memory controlled by the storage controller, so that when an accelerator accesses the storage device, data is temporarily stored in the storage device's internal buffer rather than an external system buffer memory. Claims 1–10 cover the storage device as an apparatus, Claims 11–19 cover a storage system including an accelerator with its own buffer memory, and Claim 20 covers a storage system with conditional port-routing behavior depending on whether one or two ports are present.

Q: Who owns patent US 2024/0176540 A1?

The patent is owned by Samsung Electronics Co., Ltd., headquartered in Suwon-si, Republic of Korea. The sole inventor is Beomsig Cho, also located in Suwon-si, Republic of Korea.

Q: What are the independent claims of US 2024/0176540 A1?

Claim 1 is an apparatus claim directed to a storage device comprising one or more ports, one or more physical functions, a storage controller, a plurality of nonvolatile memories, and a first buffer memory, wherein when the storage device is accessed by an external device, the first buffer memory is used by the ports and physical functions to temporarily store data for the external device. Claim 11 is a system claim directed to a storage system comprising a host device, a first accelerator that includes a first buffer memory, and a storage device connected to the host device, wherein when the storage device is accessed by the first accelerator, the accelerator's first buffer memory is used by the storage device's ports and physical functions to temporarily store data for the system. Claim 20 is a system claim directed to a storage system with a host device, an accelerator with a first buffer memory, a storage device, and a second buffer memory connected to the host device, wherein the storage device implements conditional port routing — when two ports exist the accelerator connects directly to the second port, and when only one port exists the accelerator connects through the first port and host device — with data exchange using the first or third buffer memory without using the second buffer memory.

Q: What technology does this patent cover?

This patent covers a technology called "direct storage" — a way for AI accelerators (like GPUs or specialized AI chips) to read and write data directly to a solid-state drive (SSD) without having to route the data through the computer's main memory buffer, which normally acts as an intermediary. In traditional systems, an accelerator performing AI tasks must pass data through the system's central memory, which adds latency and consumes memory bandwidth. Samsung's approach solves this by giving the SSD its own internal buffer memory and exposing dedicated communication channels (called physical functions) through its interface ports, so the accelerator can exchange data directly with the SSD's internal buffer, making AI and data-intensive workloads significantly faster. This is particularly relevant for systems using the Compute Express Link (CXL) protocol that supports high-speed, low-latency CPU-to-device communication.

Q: What IPC classifications does this patent use?

G06F 3/06 (2006.01) — Memory systems or architectures; G06F 3/0659 (2013.01) — Storage devices using solid-state media, specifically flash memory; G06F 3/0607 (2013.01) — Storage devices using solid-state media with specific interface or access method; G06F 3/0679 (2013.01) — Storage devices using solid-state media with specific transfer management.

A structural and strategic analysis of Samsung's direct storage architecture patent, covering claim architecture, drafting quality signals, critical gaps, and prosecution positioning across apparatus and storage system claim types.

US 2024/0176540 A1Filed: Jun 30, 2023Published: May 30, 2024G06F 3/06G06F 3/0659G06F 3/0607G06F 3/0679

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Spec Words

9,800

Across 6 sections

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Total Claims

3 independent · 17 dependent

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Figure Sheets

System architectures, controller diagrams, NVM structures, direct storage data flows

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Published by PatSnap Insights Team · June 3, 2026 · 13 min read Verified by PatSnap Eureka Data

Overview

Structural Overview

The detailed description dominates at approximately 59% of total words (~5,850 of ~9,800 estimated words), providing extensive embodiment coverage across 30 figures and multiple storage system variants. The claim architecture comprises 20 claims — 3 independent apparatus/system claims (Claims 1, 11, and 20) and 17 dependents — yielding a 5.67:1 dependent-to-independent ratio that is slightly above average for the G06F 3/06 IPC class. The 37-figure set provides exceptional breadth, covering multiple port configurations, multi-physical-function structures, data flow diagrams, and data center integration scenarios.

Section Word Distribution

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Figure Inventory — 37 Sheets

Figure	Description	Role
FIG. 1	Block diagram of storage system 10 showing host device 100, accelerators 200, storage device 300 with ports PT_1 to PT_N, physical functions PF_1 to PF_M, storage controller 310, NVM 320, buffer memory 330, and external buffer memory 150.Search in Eureka ↗	System architecture
FIG. 2	Block diagram of storage controller 400 showing processor 410, memory 420, FTL 430, EXT I/F 440 with CXL I/F 441, ECC engine 450, AES engine 460, and INT I/F 470.Search in Eureka ↗	Key embodiment
FIG. 3	Block diagram of nonvolatile memory 500 (NAND) showing memory cell array 510, address decoder 520, page buffer circuit 530, data I/O circuit 540, voltage generator 550, and control circuit 560.Search in Eureka ↗	Claim support
FIG. 4A	Diagram showing namespace configuration NS11–NSp1 where each nonvolatile memory NVM1–NVMp has one namespace (one-to-one correspondence).Search in Eureka ↗	Claim support
FIG. 4B	Diagram showing namespace configuration NS12–NSp2 where one namespace spans multiple nonvolatile memories NVM1–NVMp across multiple rows.Search in Eureka ↗	Claim support
FIG. 4C	Diagram illustrating a namespace NS partitioned into zones ZN1–ZNq illustrating zoned namespace (ZNS) function.Search in Eureka ↗	Claim support
FIG. 5	Block diagram of storage system 10a with multi-port storage device 300a, host device 100, first accelerator 210a, showing ports PT_1/PT_2, physical functions PF_1/PF_2, and namespaces NS1/NS2.Search in Eureka ↗	Key embodiment
FIG. 6A	Data flow diagram showing host device 100 directly exchanging data DAT1 with storage device 300a via first port PT_1 and first physical function PF_1, illustrating host-initiated direct storage access.Search in Eureka ↗	Flow diagram
FIG. 6B	Data flow diagram showing first accelerator 210a directly exchanging data DAT2 with storage device 300a via second port PT_2 and second physical function PF_2, illustrating accelerator-initiated direct storage access.Search in Eureka ↗	Flow diagram
FIG. 7	Block diagram of storage system 10b with two accelerators 210a and 220b, multi-port storage device 300b including three ports PT_1/PT_2/PT_3, three namespaces NS1/NS2/NS3, and buffer memory 330.Search in Eureka ↗	System architecture
FIG. 8	Data flow diagram for system 10b showing second accelerator 220b directly exchanging data DAT3 with storage device 300b via third port PT_3 and physical function PF_3, routing through buffer memory 330 and namespace NS3.Search in Eureka ↗	Flow diagram
FIG. 9	Block diagram of single-port storage device 300c in system 10c with single port PT_1c exposing both physical functions PF_1 and PF_2 to host device 100 and first accelerator 210c.Search in Eureka ↗	Key embodiment
FIG. 10A	Data flow diagram for system 10c showing host device 100 exchanging data DAT1 with single-port storage device 300c through port PT_1c, physical function PF_1, and buffer memory 330.Search in Eureka ↗	Flow diagram
FIG. 10B	Data flow diagram for system 10c showing first accelerator 210c exchanging data DAT2 with single-port storage device 300c through port PT_1c via host device 100 and physical function PF_2.Search in Eureka ↗	Flow diagram
FIG. 11A	Dynamic performance adjustment diagram for system 10c showing adjusted physical functions PF_1' and PF_2' when host workload increases (request RQ11 from host, RQ21 from accelerator).Search in Eureka ↗	Claim support
FIG. 11B	Dynamic performance adjustment diagram for system 10c showing adjusted physical functions PF_1'' and PF_2'' when accelerator workload increases (request RQ12 from host, RQ22 from accelerator).Search in Eureka ↗	Claim support
FIG. 12	Block diagram of system 10d combining single-port multi-physical-function storage device 300d with two accelerators 210c and 220d, adding third physical function PF_3 and third namespace NS3.Search in Eureka ↗	System architecture
FIG. 13	Data flow diagram for system 10d showing second accelerator 220d exchanging data DAT3 with storage device 300d via single port PT_1d through host device 100, physical function PF_3, and buffer memory 330.Search in Eureka ↗	Flow diagram
FIG. 14	Block diagram of system 10e combining storage configurations of FIG. 9 and FIG. 7, showing two accelerators with storage device 300e supporting three ports and three physical functions.Search in Eureka ↗	System architecture
FIG. 15	Block diagram of system 10f combining storage configurations of FIG. 5 and FIG. 12, showing two accelerators with storage device 300f supporting ports PT_1f/PT_2 and three physical functions.Search in Eureka ↗	System architecture
FIG. 16	Block diagram of storage system 20 with accelerators 700 including per-accelerator buffer memories BUF_1 to BUF_K, storage device 800 with ports/physical functions, host device 600, and external buffer memory 650.Search in Eureka ↗	System architecture
FIG. 17	Block diagram of storage controller 900 in system 20 showing processor 910, memory 920, FTL 930, EXT I/F 940, ECC engine 950, AES engine 960, and INT I/F 970 (no CXL I/F).Search in Eureka ↗	Key embodiment
FIG. 18	Block diagram of system 20a with single accelerator 710a containing buffer memory BUF_1 directly connected to multi-port storage device 800a supporting two namespaces NS1/NS2.Search in Eureka ↗	Key embodiment
FIG. 19A	Data flow diagram for system 20a showing host device 600 exchanging data DAT1 with storage device 800a via first port PT_1 and physical function PF_1, with data flowing through namespace NS1.Search in Eureka ↗	Flow diagram
FIG. 19B	Data flow diagram for system 20a showing first accelerator 710a exchanging data DAT2 with storage device 800a via second port PT_2 using accelerator's buffer memory BUF_1 and second physical function PF_2.Search in Eureka ↗	Flow diagram
FIG. 20	Block diagram of system 20b with two accelerators 710a and 720b (each with buffer memories BUF_1/BUF_2) and multi-port storage device 800b supporting three ports and three namespaces.Search in Eureka ↗	System architecture
FIG. 21	Data flow diagram for system 20b showing second accelerator 720b exchanging data DAT3 with storage device 800b using buffer memory BUF_2, third port PT_3, and third physical function PF_3.Search in Eureka ↗	Flow diagram
FIG. 22	Block diagram of system 20c with single-port storage device 800c and accelerator 710c containing buffer memory BUF_1, showing single port PT_1c supporting two physical functions PF_1/PF_2.Search in Eureka ↗	Key embodiment
FIG. 23A	Data flow diagram for system 20c showing host device 600 exchanging data DAT1 with single-port storage device 800c through port PT_1c and physical function PF_1, bypassing second buffer memory.Search in Eureka ↗	Flow diagram
FIG. 23B	Data flow diagram for system 20c showing first accelerator 710c exchanging data DAT2 with storage device 800c using buffer memory BUF_1, single port PT_1c, and physical function PF_2 through host device 600.Search in Eureka ↗	Flow diagram
FIG. 24A	Dynamic performance adjustment diagram for system 20c showing physical functions PF_1' and PF_2' when host workload increases (requests RQ11/RQ21), with buffer memory BUF_1 in accelerator 710c.Search in Eureka ↗	Claim support
FIG. 24B	Dynamic performance adjustment diagram for system 20c showing physical functions PF_1'' and PF_2'' when accelerator workload increases (requests RQ12/RQ22), with buffer memory BUF_1 in accelerator 710c.Search in Eureka ↗	Claim support
FIG. 25	Block diagram of system 20d combining single-port storage 800d with two accelerators 710c and 720d (each with buffer memories), supporting three physical functions PF_1/PF_2/PF_3.Search in Eureka ↗	System architecture
FIG. 26	Data flow diagram for system 20d showing second accelerator 720d exchanging data DAT3 with storage device 800d via single port PT_1d, host 600, and third physical function PF_3 using buffer memory BUF_2.Search in Eureka ↗	Flow diagram
FIG. 27	Block diagram of system 20e combining multi-port storage device 800e with accelerators 710c and 720b including buffer memories, where storage device has single port PT_1e and multiple physical functions.Search in Eureka ↗	System architecture
FIG. 28	Block diagram of system 20f combining storage configurations of FIGS. 5 and 25, with storage device 800f having ports PT_1f and PT_2, two accelerators 710a and 720d with buffer memories.Search in Eureka ↗	System architecture
FIG. 29	Block diagram of combined storage system 30 integrating systems 10 and 20, where storage device 1300 includes both internal buffer memory 1330 and supports accelerators 1200 with per-accelerator buffer memories BUF_1 to BUF_K.Search in Eureka ↗	System architecture
FIG. 30	Block diagram of data center 3000 showing application servers 3100 to 3100n and storage servers 3200 to 3200m connected via network 3300, each storage server including storage devices 3250 with CTRL 3251, NAND 3252, and DRAM 3253.Search in Eureka ↗	System architecture

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Claims

Claim Architecture Analysis

The claim set comprises 3 independent claims — Claims 1 and 2–10 (apparatus: storage device), Claim 11 and 12–19 (system: storage system with accelerator buffer memory), and Claim 20 (system: storage system with second buffer memory and conditional port routing) — covering two distinct apparatus types and a complex system variant. The 17 dependent claims yield a 5.67:1 ratio, which is slightly above average for G06F 3/06 hardware storage patents. Notably, the bipartite independent claim structure (storage device vs. storage system) provides enforcement coverage across both component and system-level implementations, but the absence of any method claims leaves the operational data flow aspects of direct storage unprotected.

Core inventive concept: The claims address the problem of performance degradation when accelerators (GPUs, TPUs, etc.) must access storage devices indirectly through a system buffer memory and host device, by providing a storage device with one or more physical functions exposed through one or more ports such that "when the storage device is accessed by the external device, the first buffer memory is used by the one or more ports and the one or more physical functions to temporarily store data for the external device" — enabling direct accelerator-to-storage data exchange without traversing the system buffer memory.

Independent Claim Dissection

Claim	Preamble	Transition	Key Body Elements
Claim 1	A storage device	comprising	one or more ports for electrical connection with an external device; one or more physical functions including physical resources exposed through the ports; a storage controller configured to control the device and communicate via the ports and physical functions; a plurality of nonvolatile memories controlled by the storage controller; and a first buffer memory controlled by the storage controller, wherein when the storage device is accessed by the external device, the first buffer memory is used by the ports and physical functions to temporarily store data for the external deviceSearch prior art ↗
Claim 11	A storage system	comprising	a host device; a first accelerator connected to the host device and including a first buffer memory; and a storage device connected to the host device, wherein the storage device includes one or more ports for electrical connection with at least one of the host device and the first accelerator; one or more physical functions exposed through the ports to communicate with the host device and the first accelerator; a storage controller; a plurality of nonvolatile memories; wherein when the storage device is accessed by the first accelerator, the first buffer memory is used by the ports and physical functions to temporarily store data for the storage systemSearch prior art ↗
Claim 20	A storage system	comprising	a host device; an accelerator connected to the host device including a first buffer memory for temporary storage; a storage device connected to the host device; a second buffer memory connected to the host device for temporary storage; wherein the storage device includes one or more ports; a first and second physical function exposed through the ports to communicate respectively with the host device and the accelerator; a storage controller; a plurality of nonvolatile memories; a third buffer memory; conditional port routing: when ports include both a first port (host connection) and second port (accelerator connection), first PF exposed through first port and second PF through second port with accelerator directly connected to second port; when ports include only the first port, both physical functions exposed through first port with accelerator connected via first port and host device; when accessed by accelerator, data exchange uses one of the first or third buffer memory through the second physical function, without using the second buffer memorySearch prior art ↗

Claim Dependency Tree

1 Storage device comprising ports, physical functions, storage controller, NVM, and first buffer memory for direct external device accessSearch Claim 1 prior art ↗

2 Adds: external device exchanges data using ports, physical functions, and first buffer memory without a second buffer memory located outside the storage deviceSearch in Eureka ↗

3 Adds: external device includes a host device and first accelerator; ports include first port (host) and second port (accelerator); physical functions include first PF (through first port) and second PF (through second port)Search in Eureka ↗

4 Adds: (dep. on 3) first accelerator directly connected through second port; direct data exchange via first buffer memory and second physical functionSearch in Eureka ↗

5 Adds: (dep. on 3) first namespace in first portion of NVM corresponding to first port and first PF; second namespace in second portion corresponding to second port and second PFSearch in Eureka ↗

6 Adds: (dep. on 3) external device includes a second accelerator; ports include a third port for second accelerator; physical functions include third PF through third portSearch in Eureka ↗

7 Adds: (dep. on 1) external device includes host device and first accelerator; ports include first port (host) and first port also for accelerator; physical functions include first PF (host, through first port) and second PF (accelerator, through first port)Search in Eureka ↗

8 Adds: (dep. on 7) first accelerator and storage device connected through first port and host device; data exchange via first port using first buffer memory, second PF, and host deviceSearch in Eureka ↗

9 Adds: (dep. on 7) first performance by first PF and second performance by second PF are dynamically controlled based on control of at least one of host device and first acceleratorSearch in Eureka ↗

10 Adds: (dep. on 7) external device further includes a second accelerator; physical functions further include third PF exposed through first port for second acceleratorSearch in Eureka ↗

11 Storage system comprising host device, first accelerator with first buffer memory, and storage device; accelerator's first buffer memory used during direct storage access instead of external system bufferSearch Claim 11 prior art ↗

12 Adds: (dep. on 11) accelerator exchanges data using ports and physical functions of storage device and using first buffer memory in the accelerator, without a second buffer memory outside the accelerator and storage deviceSearch in Eureka ↗

13 Adds: (dep. on 11) ports include first port (host) and second port (accelerator); physical functions include first PF (first port) and second PF (second port)Search in Eureka ↗

14 Adds: (dep. on 13) first accelerator directly connected through second port; direct data exchange via first buffer memory and second PFSearch in Eureka ↗

15 Adds: (dep. on 13) second accelerator connected to host; third port for second accelerator; third PF exposed through third portSearch in Eureka ↗

16 Adds: (dep. on 11) ports include only first port (host); both first PF and second PF exposed through first port; accelerator connected via first port and host deviceSearch in Eureka ↗

17 Adds: (dep. on 16) first accelerator connected through first port and host device; data exchange via first port using first buffer memory, second PF, and host deviceSearch in Eureka ↗

18 Adds: (dep. on 16) first and second performance by respective physical functions dynamically controlled based on control of host device and first acceleratorSearch in Eureka ↗

19 Adds: (dep. on 16) second accelerator connected to host; physical functions further include third PF exposed through first port for second acceleratorSearch in Eureka ↗

20 Storage system with host device, accelerator with first buffer memory, storage device, and second buffer memory; storage device has first and second PF with conditional port routing (multi-port vs. single-port) and third buffer memory; accelerator uses first or third buffer memory without using second buffer memorySearch Claim 20 prior art ↗

Metric	This Application	Semiconductor / Storage Norm
Total claims	20	15 – 25
Independent claim count	3	2 – 4
Dependent : Independent ratio	5.67 : 1	4 – 7 : 1
Method claims present?	No	Common
System / apparatus claims?	Yes — Claims 1, 11, 20	Always

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Drafting Quality

Drafting Quality Signals

The patent exhibits strong specification-to-claim consistency, with each of the 30+ figures directly mapping to specific embodiments described in Claims 1, 11, and 20's key limitations — particularly the conditional port-routing mechanism in Claim 20 that is supported by FIGS. 9–15 and 22–28. The most significant drafting weakness is the complete absence of method claims, leaving the operational steps of direct storage access — the reading/writing data flows illustrated in FIGS. 6A/6B, 8, 10A/10B, and 19A/19B — entirely unprotected from design-around by parties who implement the same data flow using different apparatus configurations.

✅

Antecedent Basis

Antecedent basis is clean throughout the claim set. Claim 1 introduces "one or more ports," "one or more physical functions," "a storage controller," "a plurality of nonvolatile memories," and "a first buffer memory" in its body, and all subsequent references in Claims 2–10 correctly use "the one or more ports," "the one or more physical functions," "the first buffer memory," etc. Claim 20 introduces "a first physical function and a second physical function" and consistently references them as "the first physical function" and "the second physical function" throughout its lengthy body. No antecedent basis violations were identified across all 20 claims.

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✅

Spec–Claim Consistency

The specification provides excellent support for all independent claim limitations. The "first buffer memory controlled by the storage controller" limitation in Claim 1 maps directly to buffer memory 330 described in paragraphs [0051] and FIG. 1. The conditional port-routing mechanism in Claim 20 — arguably the most complex claim element — is explicitly supported by FIGS. 9–15 (single-port embodiments) and FIGS. 5–8 (multi-port embodiments), with corresponding description in paragraphs [0113]–[0128]. The physical functions PF_1 to PF_M are described across paragraphs [0053]–[0063] and depicted in every system-level figure.

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✅

Transition Word Usage

All three independent claims use "comprising" as their transition, which is the strategically correct choice for apparatus claims in this technology domain — it leaves open the possibility of additional components and prevents easy design-around by adding elements not recited. The dependent claims also consistently use "wherein" to add limitations, which is standard practice for hardware apparatus claims. No over-narrowing through use of "consisting of" or "consisting essentially of" was observed, which would have been detrimental in this competitive storage technology space.

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✅

§112(f) Means-Plus-Function Risk

No "means for" or "step for" language appears in any of the 20 claims, and no functional label nounification risk (e.g., "a module for performing") was detected. The storage controller is recited as a structural component "configured to control an operation" — the "configured to" language is the standard hardware claim approach that avoids §112(f) interpretation while maintaining functional breadth. Physical functions are defined structurally as "including physical resources, and exposed through the one or more ports" rather than as generic functional placeholders, further reducing §112(f) exposure.

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✅

§101 Eligibility Risk

This patent presents minimal §101 risk because all independent claims are directed to concrete hardware apparatus: Claims 1 and 11 are directed to storage devices and storage systems with specific physical components (ports, NVM, storage controller, buffer memory, physical functions), and Claim 20 recites additional physical infrastructure including conditional port routing in hardware. The claims are firmly in the realm of machine claims under Alice/Mayo step one, and the specific physical function/port architecture provides ample hardware tethering. The CXL protocol reference in the detailed description (but not in claims) further grounds the technology in concrete hardware interconnect standards.

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⚠️

Dependent Claim Fallback Quality

Claims 3–6 (dependent on Claim 1) and Claims 13–15 (dependent on Claim 11) provide structurally distinct fallback positions by adding specific port configurations and namespace assignments — these are strong fallbacks that narrow the claim in specific ways an examiner could distinguish. However, Claims 2 and 12 merely restate the negative limitation ("without using a second buffer memory") that is already implied by the independent claim's mechanism, providing little additional prosecution fallback value. Claims 8 and 17 add the single-port routing through the host device, which is a genuinely distinct technical scenario well-supported by FIG. 10B, making them valuable fallbacks.

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⚠️

Abstract Quality

An examiner reading only the abstract may correctly identify the presence of a buffer memory and physical functions but may fail to appreciate the conditional port-routing innovation of Claim 20 — the most commercially significant claim — because the abstract describes only the simpler Claim 1 embodiment (storage device with ports, physical functions, storage controller, NVM, and first buffer memory for temporary storage when accessed by external device). The abstract does not mention the second or third buffer memories, the conditional port routing, or the dynamic performance adjustment mechanisms of Claims 9 and 18. A more complete abstract would have referenced these distinctions to guide examiner classification and third-party search.

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✅

Figure Support Quality

Figure support is exceptionally comprehensive across all 37 figure sheets. Every structural claim limitation in Claims 1, 11, and 20 has direct figure support: ports PT_1 to PT_N are shown in FIG. 1 and every system figure; physical functions PF_1 to PF_M are labeled in FIG. 1; buffer memory 330 appears in FIGS. 1, 5, 6A, 6B, 7, and 8; and the conditional port routing of Claim 20 is supported by the multi-port (FIG. 5) vs. single-port (FIG. 9) embodiment pairs. The dynamic performance adjustment of Claims 9 and 18 is supported by FIGS. 11A/11B and 24A/24B respectively. No claim limitation was identified without figure support.

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Scorecard

Strategic Intent Scorecard

Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.

Claim Breadth

3.8

Prosecution Defensibility

3.5

Spec–Claim Consistency

4.8

Dependent Claim Coverage

3.6

Claim Type Diversity

2.5

Figure Support Quality

4.9

Key observation: Figure Support Quality (4.9/5.0) is the strongest dimension — every claim limitation across all 20 claims maps to at least one of the 37 figure sheets, with the conditional port-routing mechanism of Claim 20 supported by a dedicated series of multi-port/single-port comparison embodiments (FIGS. 5 vs. 9, FIGS. 7 vs. 12). The weakest dimension is Claim Type Diversity (2.5/5.0), because the complete absence of method claims — despite the specification extensively describing direct storage data flows in FIGS. 6A/6B, 8, 10A/10B, 19A/19B, and 21 — means a competitor can implement the same data-routing process using different hardware components and avoid all 20 claims; a practitioner advising Samsung should consider filing a continuation with method claims directed to the step of routing data from an accelerator through a physical function of a storage device to a buffer memory of the storage device, bypassing an external system buffer memory.

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Critical Gaps

3 Critical Gaps in This Claim Set

A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.

GAP 01 · HIGHEST IMPACT

No method claims protect direct storage data flow operations

The claim set contains zero method claims despite the specification describing in detail the step-by-step data flow operations of direct storage access across FIGS. 6A/6B, 8, 10A/10B, 13, 19A/19B, 21, 23A/23B, and 26 — operations that are the core commercial value of the invention. This creates a significant design-around risk: a competitor can implement the identical data routing process (accelerator writes to physical function buffer of storage device, bypassing system buffer memory) using hardware with different structural arrangements than Claims 1, 11, or 20 and avoid infringement entirely. A stronger filing would have included at least one method claim directed to a method of directly accessing a storage device from an accelerator, the method comprising: receiving a data access request at a physical function of the storage device; routing the data through a buffer memory controlled by the storage controller via the physical function; and transferring data to or from the accelerator without using a buffer memory external to the storage device.

GAP 02 · HIGH IMPACT

Dynamic performance allocation claims depend on structural claims, limiting enforcement

Claims 9 and 18, which cover the commercially important dynamic/adaptive performance allocation between physical functions ("first performance by the first physical function and second performance by the second physical function are dynamically controlled based on a control of at least one of the host device and the first accelerator"), appear only as dependent claims of Claims 7 and 16 respectively, which are themselves dependent on Claims 1 and 11. This chain dependency means the dynamic performance feature — supported by the dedicated FIGS. 11A, 11B, 24A, and 24B — can only be asserted as an infringement theory when all parent claim limitations are also met, substantially limiting enforcement flexibility. A stronger filing would have promoted the dynamic performance allocation mechanism to an independent claim, reciting only the minimum structural context needed to support the limitation.

GAP 03 · HIGH IMPACT

No CRM or firmware claims on FTL and storage controller operations

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3 Critical Gaps in This Claim Set

See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.

No method claims on direct storage access Dynamic performance allocation only in dependent claims No CRM claims on FTL and firmware operations

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Frequently asked questions

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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.

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Patent Drafting Analysis of Samsung Electronics’ Direct Storage Device and Storage System | US 2024/0176540 A1

Patent Drafting Analysis of Samsung Electronics' Direct Storage Device and Storage System | US 2024/0176540 A1