Patent Drafting Analysis of SeeQC Inc.’s SFQ Flux Bias System for Superconducting Quantum Circuits | US 12,087,503 B2
Patent Drafting Analysis of SeeQC Inc.'s SFQ Flux Bias Control System for Superconducting Quantum Circuits | US 12,087,503 B2
A structural and strategic analysis of SeeQC's granted patent covering SFQ-based magnetic flux biasing for quantum qubits and couplers, examining claim architecture, drafting quality, critical coverage gaps, and prosecution positioning across 30 claims.
Spec Words
18,400
Across 6 sections
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Total Claims
30
3 independent · 27 dependent
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Figure Sheets
28
Circuit schematics, signal waveforms, system block diagrams
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Published by PatSnap Insights Team · · 13 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 68% of total specification words (~12,500 words), with the Summary section providing a notably substantial ~3,500 words of additional claim-supporting disclosure — an unusual balance that signals deliberate effort to broaden written description support. The patent presents 30 claims structured around 3 independent claims: Claims 1 (apparatus/system), 29 (second apparatus/system), and 30 (method), yielding a 9:1 dependent-to-independent ratio well above the semiconductor/quantum computing norm. The 28 drawing sheets cover circuit-level schematics, time-domain signal waveforms, block diagrams for single- and multi-qubit systems, and a physical chip layout with experimental measurements, providing comprehensive visual support for the core embodiments.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 28 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1 | Conceptual diagram of a flux biasing circuit showing SFQ circuits to add and remove flux, inductors L_in and L_out, and mutual coupling M to a Qubit/Coupler.Search in Eureka ↗ | Key embodiment |
| FIG. 2 | Refined flux biasing circuit using Josephson Transmission Lines (JTLs) in each of the two SFQ control channels for add and remove flux.Search in Eureka ↗ | Key embodiment |
| FIG. 3 | Scalable flux biasing circuit using parallel JTLs (n stages) for both add-flux and remove-flux SFQ control channels to increase stored fluxons.Search in Eureka ↗ | Key embodiment |
| FIG. 4 | Simulation showing SFQ pulses to increase flux (left), SFQ pulses to decrease flux (center), and resulting integrated flux on Qubit/Coupler over time.Search in Eureka ↗ | Claim support |
| FIG. 5 | Simulation of arbitrary time-varying flux biasing showing interleaved SFQ increase and decrease pulses producing a non-monotonic flux waveform on the Qubit/Coupler.Search in Eureka ↗ | Claim support |
| FIG. 6 | Circuit diagram for coarse flux biasing using flux pumps connected to SFQ add-flux and remove-flux controls with inductive transformer coupling to Qubit/Coupler.Search in Eureka ↗ | Key embodiment |
| FIG. 7 | Two-stage coarse and fine-tune biasing circuit with separate SFQ circuits for coarse (L_in1, M1) and fine-tune (L_in2, M2) flux control channels to a single Qubit/Coupler.Search in Eureka ↗ | Key embodiment |
| FIG. 8 | Flux reset circuit using a SQUID in series with the inductive storage loop to dissipate stored flux and reset the integrated magnetic flux to zero.Search in Eureka ↗ | Claim support |
| FIG. 9A | Block diagram for single-qubit gate operation with time-variable flux biasing, showing Central Control Unit, SFQ Pulse Pattern Generation, SFQ Amplitude Control, SFQ-Qubit Coupler, and Tunable Qubit.Search in Eureka ↗ | System architecture |
| FIG. 9B | Block diagram for single-qubit gate operation using flux bias pulses (FBP) with SFQ FBP Amplitude Control and SFQ FBP Ramp Control feeding an SFQ FBP-Qubit Coupler.Search in Eureka ↗ | System architecture |
| FIG. 10A | Block diagram for multi-qubit gate operation with time-variable flux biasing of two tunable qubits and a coupler, coordinated by a Central Control Unit with SFQ Flux Bias and SFQ Coupler Control.Search in Eureka ↗ | System architecture |
| FIG. 10B | Block diagram for multi-qubit operation using pulse-rate-variable flux bias pulses (FBP) with SFQ FBP Amplitude and Ramp Control for two coupled tunable qubits and a coupler.Search in Eureka ↗ | System architecture |
| FIG. 11 | Timing diagram of single qubit operation combining SFQ pulses to a flux tuner for qubit energy and SFQ pulse train applied directly to the qubit for state rotation.Search in Eureka ↗ | Claim support |
| FIG. 12A | Block diagram of prototype SFQ flux bias circuit using counters, switches (Sw), amplifying JTLs (AJTL), and inductive coupling inductor L1 to qubit Q via mutual inductance Lm.Search in Eureka ↗ | Key embodiment |
| FIG. 12B | Flux bias circuit with closed-loop feedback employing a sensor, performance indicator, comparator, setpoint, and controller to regulate flux on qubit Q via AJTL switching.Search in Eureka ↗ | Claim support |
| FIG. 12C | Circuit diagram of an SFQ flux bias circuit to produce net-zero flux bias pulses for fluxonium control using TFF, counter, ND switches, and SYNC circuit during calibration.Search in Eureka ↗ | Key embodiment |
| FIG. 12D | Simplified low-hardware-overhead SFQ flux bias circuit for net-zero flux pulses using a dc/SFQ converter with slow ramp input, ND switch, counter, and TFF.Search in Eureka ↗ | Key embodiment |
| FIG. 12E | Closed-loop flux bias circuit for transmon qubit with homodyne receiver (mixer, detector, comparison circuit, deadband controller) and suppress logic controlling SFQ switches.Search in Eureka ↗ | Claim support |
| FIG. 13 | Schematic of an amplifying JTL (AJTL) with multiple parallel Josephson junctions showing SFQ input, bias current input, and amplified output current.Search in Eureka ↗ | Claim support |
| FIG. 14A | Block diagram of a relaxation oscillator flux pump with two ROS modules triggered by On/Off signals, driving JTLs connected to qubit Q via inductive coupling L1 and Lm.Search in Eureka ↗ | Key embodiment |
| FIG. 14B | Detailed circuit schematic of a relaxation oscillator (ROS) comprising hysteretic Josephson junction Jm2, inductors L1 and L2, resistors R2 and R3, and STDIN input modulator M1.Search in Eureka ↗ | Key embodiment |
| FIG. 14C | Graph of relaxation oscillator simulation showing total flux output (solid curve) and voltage output (dotted curve) versus frequency, demonstrating oscillator operating range.Search in Eureka ↗ | Other |
| FIG. 15 | Block diagram of a serially programmable NDRO register with N TFF stages (A0-A6) clocked by HF Clock, Load input, and serial data/clock input for programmable pulse counting.Search in Eureka ↗ | Claim support |
| FIG. 16A | Top-level schematic of a prototype SFQ flux bias circuit showing bipolar flux channels (Flux ON/Flux OFF), flux bias drivers (FB_DRV mfb1/mfb2), SPL, JTL, and output flux inductor LFB.Search in Eureka ↗ | Key embodiment |
| FIG. 16B | Schematic of the flux generating circuit from FIG. 16A showing amplifying JTL (FB_AJTL), FB_AMP, switch (SW_SPL1), and counter DIVX16 for pulse frequency division.Search in Eureka ↗ | Key embodiment |
| FIG. 16C | Schematic of the switch circuit from FIG. 16B showing SPL, JTL elements (Mt3-Mt6), rs_ndro NDRO cell, DFFX2 synchronizer (Sync) for controlled SFQ routing.Search in Eureka ↗ | Key embodiment |
| FIG. 16D | Schematic of the synchronizer component of the switch from FIG. 16C, comprising SW_DFF D-flip-flops (MD1, MD2), SW_SPL1, and JTL elements for two-channel synchronization.Search in Eureka ↗ | Key embodiment |
| FIG. 17 | Physical circuit layout photograph of a prototype SFQ flux bias chip showing Flux on driver (171), counter (172), JTL current amplifier (173), and Flux off driver with niobium Josephson junctions.Search in Eureka ↗ | Other |
| FIG. 18 | Simulation of the prototype SFQ flux bias circuit showing output current, clock, left and right flux pulses, and Right On/Right Off/Left On/Left Off control signal timing.Search in Eureka ↗ | Claim support |
| FIG. 19 | Experimental measurements of the prototype SFQ flux bias circuit showing clock signal, flux pump signal (stepped levels), and DC SQUID flux-voltage modulation confirming circuit functionality.Search in Eureka ↗ | Other |
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Claims
Claim Architecture Analysis
The patent presents 3 independent claims: Claim 1 (apparatus — magnetic flux control system), Claim 29 (second apparatus — magnetic flux control system with different structural starting point), and Claim 30 (method), providing system and method coverage but lacking a separate computer-readable medium or CRM claim. The dependent-to-independent ratio of 9:1 exceeds the typical quantum computing hardware norm of approximately 6:1, with the 27 dependent claims providing extensive layered fallback. The dual-system structure (Claims 1 and 29) represents a strategic drafting choice to capture both transformer-coupled and coupling-circuit embodiments, though the absence of explicit CRM claims leaves potential software-side enforcement coverage on the table.
Core inventive concept: Claims 1 and 30 address the problem of slow, inaccurate flux biasing in superconducting quantum computers by using a superconducting circuit to convert sequences of single-flux-quantum (SFQ) pulses into integrated magnetic flux via a superconducting inductor, controlled by a Josephson-junction-based control system that selectively adds or removes SFQ pulses to define and maintain a precise target magnetic flux coupled to qubits or couplers. The inventive mechanism — as recited across Claims 1, 29, and 30 — combines the digital precision and cryogenic compatibility of SFQ logic with an integrating superconducting storage loop to achieve arbitrary-amplitude, time-varying flux biasing without the power and bandwidth limitations of conventional microwave or current-bias control lines.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A magnetic flux control system | comprising | superconducting circuit converting each SFQ pulse into magnetic flux; superconducting inductor integrating flux to define integrated magnetic flux; control system comprising plurality of Josephson junctions configured to generate at least one output control signal comprising at least one sequence of SFQ pulses adapted to selectively change the integrated magnetic fluxSearch prior art ↗ |
| Claim 29 | A magnetic flux control system | comprising | at least one superconducting circuit generating SFQ pulses; coupling circuit configured to couple SFQ pulses into a corresponding magnetic flux; superconducting inductor integrating magnetic flux to define integrated magnetic flux; qubit having resonance frequency dependent on integrated magnetic flux; sensor with sensor output; control system comprising plurality of Josephson junctions configured to control value of integrated magnetic flux dependent on sensor outputSearch prior art ↗ |
| Claim 30 | A magnetic flux control method for controlling a superconducting system | comprising | defining a target magnetic flux; controlling the superconducting circuit to produce SFQ pulses for monotonically changing the integrated magnetic flux to reduce difference between target flux and integrated flux; controlling the superconducting circuit to cease production of SFQ pulses for monotonically changing the integrated magnetic flux when integrated flux ceases to be monotonically changed; wherein said controlling to cease is dependent on a value of the integrated magnetic fluxSearch prior art ↗ |
Claim Dependency Tree
1 Magnetic flux control system: SFQ-to-flux conversion circuit + integrating superconducting inductor + Josephson junction control system generating SFQ pulse sequencesSearch Claim 1 prior art ↗
2 Adds: quantum computing circuit with qubit and tunable qubit coupler having physical property tunable dependent on integrated magnetic fluxSearch in Eureka ↗
3 Adds: physical property comprises microwave resonance, energy, and phase of the qubitSearch in Eureka ↗
4 Adds: control system configured to control dynamic variation of physical property of qubit and tunable qubit couplerSearch in Eureka ↗
5 Adds: flux control system and qubit/coupler in first and second integrated circuits on common substrateSearch in Eureka ↗
6 Adds: first and second integrated circuits on separate substrates with flip-chip geometrySearch in Eureka ↗
7 Adds: tunable qubit coupler comprises switched qubit coupler for selectively controlling presence/absence of interaction of plurality of qubitsSearch in Eureka ↗
8 Adds: pair of output ports producing first signal to increase and second signal to decrease integrated magnetic fluxSearch in Eureka ↗
9 Adds: frequency mixer and detector configured to receive qubit output and produce input control signal for control systemSearch in Eureka ↗
10 Adds: superconducting oscillator configured to generate microwave signal interacting with a qubitSearch in Eureka ↗
11 Adds: superconducting inductor coupled to transmon qubit circuit; control system defines first and second microwave resonant frequencies in successive quantum calculation periodsSearch in Eureka ↗
12 Adds: superconducting inductor coupled to transmon qubit circuit; control system tunes microwave resonance dependent on microwave resonance state of transmon qubit circuitSearch in Eureka ↗
13 Adds: first input port for reference frequency signal, second input port for microwave resonance signal, comparing circuit producing comparison output to control integrated magnetic fluxSearch in Eureka ↗
14 Adds: control system receives input signal from qubit representing calculation state during quantum computing and controls flux selectively dependent on that calculation stateSearch in Eureka ↗
15 Adds: error input port and memory to persistently store calibration value; control system produces output control signal dependent on persistently stored calibration valueSearch in Eureka ↗
16 Adds: superconducting circuit configured to reset the integrated magnetic flux to a predetermined valueSearch in Eureka ↗
17 Adds: control system produces at least two types of SFQ pulse sequences with different flux-change amounts; receives input control signal representing amount of changeSearch in Eureka ↗
18 Adds: control system produces at least two different types of output control signals comprising SFQ pulse sequences with different positive whole numbers of SFQ pulsesSearch in Eureka ↗
19 Adds: counter responsive to target value; superconducting transformer primary inductor coupled to superconducting inductor as secondary inductor; first and second terminal opposite polarity pulsesSearch in Eureka ↗
20 Adds: control system receives feedback signal based on integrated magnetic flux magnitude; gate configured to cease SFQ pulse sequences when feedback indicates sufficient correctionSearch in Eureka ↗
21 Adds: feedback signal input; control system produces: continuous series of first-type SFQ pulses for increasing flux, or second-type for decreasing flux, or no-net-SFQ-pulses outputSearch in Eureka ↗
22 Adds: counter receiving target value; selectively increments on first-type SFQ pulses; decrements on second-type; suppresses net SFQ pulses at error margin of target valueSearch in Eureka ↗
23 Adds: reset circuit comprising reset inductor coupled to SQUID having critical current in series with superconducting inductor; current sufficient to drive SQUID above critical currentSearch in Eureka ↗
24 Adds: control system configured to implement at least one of phase locked loop control and frequency locked loop controlSearch in Eureka ↗
25 Adds: control system configured to receive a photonic input control signalSearch in Eureka ↗
26 Adds: input port configured to receive at least one feedback signal relating to magnitude of the integrated magnetic fluxSearch in Eureka ↗
27 Adds: qubit whose state is represented by phase and amplitude on Bloch sphere, coupled to integrated magnetic flux; phase and amplitude responsive to at least one output control signalSearch in Eureka ↗
28 Adds: superconducting quantum interference device responsive to integrated magnetic flux producing magnetometer output; control system input responsive to magnetometer outputSearch in Eureka ↗
29 Second magnetic flux control system: SFQ generation + coupling circuit + integrating superconducting inductor + frequency-tunable qubit + sensor feedback + Josephson junction control systemSearch Claim 29 prior art ↗
30 Magnetic flux control method: define target flux; control SFQ circuit to monotonically change integrated flux toward target; cease when integrated flux reaches target valueSearch Claim 30 prior art ↗
| Metric | This Application | Quantum Computing / Semiconductor Norm |
|---|---|---|
| Total claims | 30 | 20 – 30 |
| Independent claim count | 3 | 2 – 4 |
| Dependent : Independent ratio | 9.0 : 1 | 5 – 8 : 1 |
| Method claims present? | Yes — Claim 30 | Common |
| System / apparatus claims? | Yes — Claims 1 and 29 | Always |
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Drafting Quality
Drafting Quality Signals
The patent demonstrates strong antecedent basis discipline and robust figure-to-claim mapping across its 28 drawing sheets, with FIGs. 1–3, 9A–10B, and 12A–12E providing detailed structural support for substantially all independent claim limitations. The primary weakness is the absence of a CRM or software-claim track, which creates a prosecution and enforcement gap given that the SFQ control logic described in Claims 14, 15, 21, and 22 encompasses programmable digital control functions that could have been protected across multiple claim types.
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Antecedent Basis
The claims exhibit clean antecedent basis throughout, with no apparent improper use of "the" without prior introduction. For example, Claim 1's "the superconducting circuit," "the magnetic flux," and "the control system" all have proper antecedents in the preamble. Claim 19's reference to "the superconducting circuit" and "the superconducting inductor" correctly trace back to Claim 1. No antecedent basis issues were identified across Claims 1–30.
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Spec–Claim Consistency
Specification support is strong for all three independent claims. FIG. 1 and the detailed description at col. 52 directly map to Claim 1's three-element combination (superconducting circuit, superconducting inductor, control system). FIG. 12B and col. 53–54 support Claims 20 and 21's feedback gate limitation. FIG. 9A and col. 34 provide written description for the multi-qubit system aspects of Claims 2 and 4. Claim 30's method steps are directly supported by col. 36's "Summary of the Invention" method recitation.
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Transition Word Usage
All three independent claims use "comprising," the open-ended transition appropriate for patent claims in hardware-intensive quantum computing inventions — this is the optimal choice here, permitting embodiments with additional components (e.g., feedback sensors, oscillators) without foreclosing infringement. No restrictive "consisting of" or "consisting essentially of" transitions appear in the claims. The choice to use "comprising" uniformly across Claims 1, 29, and 30 is strategically sound given the breadth of disclosed embodiments.
✅
§112(f) Means-Plus-Function Risk
No "means for" or "step for" language appears in Claims 1–30, eliminating direct §112(f) exposure. Functional language in Claims 9 ("configured to receive an output of at least one qubit and produce an input control signal"), 13 ("comparison output configured to control"), and 21 ("output representing no net single-flux-quantum pulses") is paired with structural recitations (frequency mixer/detector, comparing circuit, control system with Josephson junctions), adequately grounding the functional limitations. The drafting successfully avoids means-plus-function traps while preserving broad functional scope.
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§101 Eligibility Risk
This patent carries minimal §101 Alice/Mayo exposure: all three independent claims are firmly grounded in physical hardware — specifically, superconducting circuits, Josephson junctions, and superconducting inductors operating at cryogenic temperatures. Claim 1's recitation of a superconducting circuit physically converting SFQ voltage pulses into magnetic flux via an integrating inductor is unambiguously directed to a machine, not an abstract idea. Even the feedback-intensive dependent Claims 20–22 are tied to physical counting circuits and superconducting gate elements, making §101 rejection unlikely.
⚠️
Dependent Claim Fallback Quality
A risk of reduced fallback quality arises from the large number of dependent claims that add incremental feature layers rather than fundamentally distinct inventive concepts — for example, Claims 3, 4, 11, and 12 all depend on Claim 2 and address increasingly specific transmon qubit configurations, creating overlapping fallback that a skilled design-around could sidestep by using a non-transmon qubit type. However, Claims 15 (persistent calibration memory), 19 (transformer with opposite-polarity pulse terminals), 22 (counter with increment/decrement/suppress logic), and 23 (SQUID-based reset circuit) each add genuinely distinct technical limitations not captured elsewhere and represent strong fallback positions.
⚠️
Abstract Quality
An examiner reading only the abstract would correctly identify the general domain (superconducting quantum computer flux biasing using SFQ technology) but may not immediately identify the key novel contribution — the use of a superconducting storage loop with a Josephson junction control system to integrate SFQ pulses into arbitrary-amplitude time-varying flux bias signals. The abstract states the method "enables arbitrary-amplitude time-varying flux biasing" which is informative, but omits the critical structural mechanism of the integrating superconducting inductor and the pulse-counting control system. A stronger abstract would have explicitly named the storage loop and bidirectional SFQ control architecture.
✅
Figure Support Quality
Figure support is comprehensive and specifically tied to claim limitations. FIG. 1 supports Claim 1's three core structural elements (L_in/superconducting circuit, M/superconducting inductor, SFQ add/remove circuits/control system). FIG. 12B supports the feedback limitation of Claims 20 and 26 through the sensor-performance indicator-setpoint-controller feedback chain. FIG. 8 directly supports Claim 23's SQUID-based reset circuit. FIG. 17's physical layout photograph and FIG. 19's experimental measurements provide important enablement evidence. No independent or major dependent claim limitation appears to lack corresponding figure support.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
4.2
Prosecution Defensibility
4.4
Spec–Claim Consistency
4.6
Dependent Claim Coverage
3.8
Claim Type Diversity
3.2
Figure Support Quality
4.7
Key observation: The highest-scoring dimension is Figure Support Quality (4.7/5.0): the 28 drawing sheets provide exceptionally detailed coverage mapping to essentially every structural limitation across all 30 claims, including the physical chip layout (FIG. 17) and experimental measurements (FIG. 19) that are rare in quantum hardware patents and strengthen enablement arguments. The lowest-scoring dimension is Claim Type Diversity (3.2/5.0): while the patent covers two apparatus claims (Claims 1 and 29) and one method claim (Claim 30), the absence of computer-readable medium claims and software-claim tracks represents a meaningful enforcement gap given that the SFQ digital control algorithms recited in Claims 14, 15, 21, and 22 would naturally lend themselves to CRM protection — practitioners should consider a continuation filing to add CRM claims targeting the programmable SFQ control pattern generation described in FIGS. 9A, 9B, and 15.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
Missing CRM claims for SFQ control logic No independent multi-qubit array claim Unprotected pulse pattern generation circuit
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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