Patent Drafting Analysis of Seoul National University R&DB Foundation’s On-Chip Training Neuromorphic Architecture | US 12,099,919 B2
Patent Drafting Analysis of Seoul National University R&DB Foundation's On-Chip Training Neuromorphic Architecture | US 12,099,919 B2
A structural and strategic analysis of US 12,099,919 B2, examining claim architecture, drafting quality, critical gaps, and prosecution positioning for this flash-based neuromorphic on-chip training system.
Spec Words
7,200
Across 5 sections
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Total Claims
13
1 independent · 12 dependent
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Figure Sheets
12
System architecture, circuits, synapse arrays, neuron layers
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Published by PatSnap Insights Team · · 13 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 67% of total words (~4,800 of ~7,200), providing extensive circuit-level and operational detail across two distinct embodiments. The claim set is compact with only 13 claims — a single independent claim (Claim 1) supported by 12 dependent claims — which concentrates prosecution risk on a single claim root. Figure coverage is comprehensive across 12 sheets (FIGs. 1A–14B), spanning system-level block diagrams, individual circuit schematics for forward neurons, backward neurons, memory layers, and error calculation circuits, providing strong written description support.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 12 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1A | Diagram of a hardware-based neural network showing input, hidden, and output neuron layers connected by synapse arrays.Search in Eureka ↗ | Other |
| FIG. 1B | Table mapping software neural network parameters (input, weight, VMM) to hardware synapse array equivalents (voltage, conductance).Search in Eureka ↗ | Other |
| FIG. 2 | Configuration block diagram of the first-embodiment neuromorphic system showing input layer 10, synapse arrays 20–22, neuron layers 30–31, final neuron layer 39, and error calculation circuit 40 with forward/backward/weight-update signal flows.Search in Eureka ↗ | System architecture |
| FIG. 3A | Block diagram of the first (input-side) charge-storage-layer-based synapse array showing input X and memory signal M inputs and output O.Search in Eureka ↗ | Claim support |
| FIG. 3B | Schematic of the first synapse array (3×3 positive conductance G+ configuration) with input switching element S1 and output switching element S2.Search in Eureka ↗ | Claim support |
| FIG. 3C | Schematic of the first synapse array (2×2 negative conductance G- configuration) showing smaller crossbar arrangement with switching elements S1 and S2.Search in Eureka ↗ | Claim support |
| FIG. 4A | Block diagram of second and subsequent synapse arrays with inputs X, memory M, backward signal BO, and outputs BX and UX illustrating bidirectional operation.Search in Eureka ↗ | Claim support |
| FIG. 4B | Schematic of second synapse array positive conductance configuration (3×3) showing X, BO, and M interleaved row inputs and switching elements.Search in Eureka ↗ | Claim support |
| FIG. 4C | Schematic of second synapse array negative conductance configuration (3×3) showing the complementary crossbar arrangement for backward propagation.Search in Eureka ↗ | Claim support |
| FIG. 5A | Block diagram of forward neuron layer 300 receiving input O and outputting firing spike signal X and memory output.Search in Eureka ↗ | Claim support |
| FIG. 5B | Circuit diagram of the forward neuron layer 300 showing current mirror circuit 302 and firing circuit 304 with multiple V_input branches and current summation nodes.Search in Eureka ↗ | Key embodiment |
| FIG. 5C | Detailed circuit of firing circuit 304 showing membrane capacitor C1 (Cmem), switching elements M1–M6, inverters, and capacitor C2 implementing the integrate-and-fire mechanism.Search in Eureka ↗ | Key embodiment |
| FIG. 6 | Block diagram of memory layer 310 receiving forward neuron output X and outputting firing information M and conductance information G.Search in Eureka ↗ | Claim support |
| FIG. 7A | Block diagram of error calculation circuit 40 receiving forward neuron output X3 and target signal T to output error value BO3.Search in Eureka ↗ | Claim support |
| FIG. 7B | Circuit diagram of error calculation circuit 40 implemented with two FET elements connected in series comparing target T and output X3 signals.Search in Eureka ↗ | Key embodiment |
| FIG. 8A | Block diagram of backward neuron layer 3 (final neuron layer) showing inputs BO3 and outputs BX3 and UX3.Search in Eureka ↗ | Claim support |
| FIG. 8B | Block diagram of intermediate backward neuron layer 2 showing inputs Gn and BOn and outputs BXn and UXn for hidden layer backward propagation.Search in Eureka ↗ | Claim support |
| FIG. 8C | Block diagram of first backward neuron layer 1 showing inputs G1 and BO1 and output UX1 for the first layer weight update signal generation.Search in Eureka ↗ | Claim support |
| FIG. 9A | Circuit diagram of the pulse width modulation (PWM) circuit of backward neuron 320 including sawtooth wave generator 900, differential amplifier 910, and level shifter 920.Search in Eureka ↗ | Key embodiment |
| FIG. 9B | Circuit diagram showing input voltage V of the backward neuron configured with PWM circuit, illustrating membrane capacitor charging from backward weighted value current and error generation signal Gn.Search in Eureka ↗ | Key embodiment |
| FIG. 10 | Diagram illustrating the on-chip training method for weight optimization showing neuron firing spike signals H1/H2, activation values X1/X2, error delta, and timing over T time steps.Search in Eureka ↗ | Flow diagram |
| FIG. 11 | Diagram showing bias conditions for program and erase operations applied to the synapse array cells (Cell1–Cell4) using weight update signals M and UX in the weighted value update phase.Search in Eureka ↗ | Claim support |
| FIG. 12 | Block diagram of the second-embodiment neuromorphic system showing charge-storage-layer-based synapse arrays 1–3, neuron layers with forward neurons, memory layers, and backward neurons, with detailed positive/negative error signal paths.Search in Eureka ↗ | System architecture |
| FIG. 13A | Block diagram of the final-neuron-layer backward neuron in the second embodiment showing inputs BO3 and outputs BX3+, BX3-, UX3+, UX3-.Search in Eureka ↗ | Claim support |
| FIG. 13B | Circuit diagram of second-embodiment final-layer backward neuron showing two-inverter first path for BX3+/UX3+ and single-inverter second path for BX3-/UX3- signals.Search in Eureka ↗ | Key embodiment |
| FIG. 14A | Block diagram of intermediate neuron layer backward neuron in second embodiment showing inputs Gn, BOn and outputs BXn+, BXn-, UXn+, UXn-.Search in Eureka ↗ | Claim support |
| FIG. 14B | Circuit diagram of intermediate neuron layer backward neuron in second embodiment showing current mirror input stages for BO signals and inverter-based output paths for differential BXn+/BXn- and UXn+/UXn- signals.Search in Eureka ↗ | Key embodiment |
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Claims
Claim Architecture Analysis
The patent contains a single independent claim (Claim 1) of the system/apparatus type, supported by 12 dependent claims, yielding an unusually high dependent-to-independent ratio of 12:1 — far above the typical semiconductor/AI hardware norm of 4–8:1 — which concentrates all prosecution risk on a single claim root. Claim 1 is a neuromorphic system claim covering the complete architecture of synapse arrays, forward/backward neuron layers, memory, and error calculation circuit. The filing strategy relies entirely on apparatus-type protection, with no method or CRM claim variants to guard alternative design-around approaches.
Core inventive concept: Claim 1 solves the power and area inefficiency of prior-art neuromorphic on-chip training systems (which required Op-Amps, ADCs, and DACs) by implementing a complete neuromorphic training pipeline — forward propagation, backward propagation, and weighted value update — entirely in hardware using synapse devices configured with a gated Schottky diode (GSD) having a charge storage layer or a nonvolatile memory device, where conductances represent neural network weights and are directly updated without digital conversion overhead.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A neuromorphic system enabling on-chip training | comprising | one or more synapse arrays with cross-bar arranged synapse devices having preset conductance; input layer supplying input to first synapse array; final neuron layer with forward neuron (forward propagation) and backward neuron (backward propagation) connected to last synapse array output; one or two or more neuron layers with forward neuron, backward neuron, and memory storing weighted value update signals arranged between remaining synapse arrays; error calculation circuit detecting error value between target signal and final neuron layer output signal; synapse devices configured with gated Schottky diode (GSD) having charge storage layer or nonvolatile memory device with charge storage layerSearch prior art ↗ |
Claim Dependency Tree
1 Neuromorphic system enabling on-chip training — synapse arrays (cross-bar, GSD/nonvolatile), input layer, final neuron layer (fwd+bwd neuron), intermediate neuron layers (fwd+bwd neuron+memory), error calculation circuitSearch Claim 1 prior art ↗
2 Adds: forward neuron in neuron layer includes capacitor charged by forward weighted value current, switching element outputting firing spike signal when threshold exceeded, spike output to synapse array and memorySearch in Eureka ↗
3 Adds: forward neuron of final neuron layer includes capacitor and switching element outputting firing spike signal to error calculation circuit output terminalSearch in Eureka ↗
4 Adds: backward neuron (neuron layer and final neuron layer) includes differential amplifier outputting difference between synapse/error circuit voltage input and preset reference pulse, level shifter adjusting output voltage, error signal generated by PWM modulating backward weighted valueSearch in Eureka ↗
5 Adds: (depends on Claim 4) backward neuron of neuron layer receives backward weighted value current from synapse array and error generation signal from memory; generates PWM error signal using error generation signalSearch in Eureka ↗
6 Adds: synapse array further includes input switching element (switching input to forward neuron output, memory output, or backward neuron input of pre-stage) and output switching element (switching output to forward/backward neuron input of post-stage)Search in Eureka ↗
7 Adds: (depends on Claim 6) controller controlling input/output switching elements through all three phases: forward propagation, backward propagation, weighted value updateSearch in Eureka ↗
8 Adds: memory of neuron layer stores first information (last time step firing, used as weighted value update signal) and second information (entire time steps firing, used as error generation signal)Search in Eureka ↗
9 Adds: backward neuron (neuron layer and final neuron layer) includes first path (two inverters in series) for positive error signal and second path (single inverter) for negative error signal; positive signal to pre-stage synapse via first path, negative via second pathSearch in Eureka ↗
10 Adds: (depends on Claim 9) backward neuron of neuron layer receives backward weighted value current and error generation signal from memory; sequentially outputs positive and negative error signals to pre-stage synapse using error generation signalSearch in Eureka ↗
11 Adds: synapse array further includes input switching element (switching to forward neuron output or backward neuron input of pre-stage) and output switching element (switching to forward neuron input or backward neuron output of post-stage)Search in Eureka ↗
12 Adds: (depends on Claim 11) controller controlling input/output switching elements through all three phases of operationSearch in Eureka ↗
13 Adds: memory of neuron layer stores information on whether neuron is fired during entire time steps for one image input (used as error generation signal for backward neuron)Search in Eureka ↗
| Metric | This Application | Semiconductor / AI Hardware Norm |
|---|---|---|
| Total claims | 13 | 15 – 25 |
| Independent claim count | 1 | 2 – 5 |
| Dependent : Independent ratio | 12.00 : 1 | 4 – 8 : 1 |
| Method claims present? | No | Common |
| System / apparatus claims? | Yes — Claim 1 | Always |
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Drafting Quality
Drafting Quality Signals
Claim 1 benefits from specific hardware limitations — the GSD/nonvolatile memory device limitation anchors §101 eligibility, and the cross-bar synapse array plus three-phase operational architecture is well-supported by FIGs. 2–14. However, the entire claim set depends from a single independent claim, creating a critical fragility where any invalidation of Claim 1 collapses all 12 dependent claims simultaneously, and the complete absence of method claims leaves straightforward design-around opportunities for any actor implementing the same training algorithm with different hardware topology.
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Antecedent Basis
The claim set is clean on antecedent basis throughout all 13 claims. Claim 1 introduces "one or more synapse arrays," "an input layer," "a final neuron layer," "one or two or more neuron layers," and "an error calculation circuit" — each element is properly introduced before being referenced with "the" in dependent claims (e.g., Claims 2–5 reference "the forward neuron of the neuron layer" and "the forward neuron of the final neuron layer" correctly). No §112(b) indefiniteness risk from antecedent basis errors is present.
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Spec–Claim Consistency
Every independent limitation in Claim 1 maps precisely to specific figures and paragraphs. The synapse array cross-bar arrangement is supported by FIGs. 3B, 3C, 4B, 4C and the detailed description at col. 7–8. The GSD/nonvolatile memory device limitation is described at col. 7 ("may be configured with a gated Schottky diode (GSD) including a charge storage layer..."). The error calculation circuit is covered by FIGs. 7A–7B. The memory layer storing weighted value update signals is supported by FIG. 6 and col. 9–10. Written description support is robust and traceable for all claim elements.
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Transition Word Usage
All 13 claims correctly use "comprising" as the transition word, which is the maximally open-ended choice and allows infringement even when additional components are present. The selection of "comprising" is particularly strategic here since neuromorphic systems in practice routinely include supplemental control circuits (MCU, DAC calibration) not recited in the claims — an "consisting of" choice would have been fatal. No missed opportunities for "consisting essentially of" are apparent given the hardware nature of the claims.
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§112(f) Means-Plus-Function Risk
Claims 6 and 11 recite "an input switching element configured to switch an input terminal" and "an output switching element configured to switch an output terminal" — the "element configured to" formulation can be construed as functional claiming under §112(f) if the structural identity of the switching element is not sufficiently defined. While FIGs. 3B–4C show S1 and S2 switching elements, the claims do not recite their structural form (transistor, multiplexer, etc.), creating a risk that a court could apply §112(f) and limit the claim scope to the specific S1/S2 structures shown in the figures. A stronger filing would have recited the switching element's structural type explicitly.
✅
§101 Eligibility Risk
The patent carries low §101 eligibility risk because Claim 1 is fundamentally a hardware apparatus claim directed to a specific neuromorphic circuit architecture rather than an abstract idea or mathematical algorithm. The GSD/nonvolatile memory device limitation, the cross-bar synapse array, and the explicit hardware components (forward neuron, backward neuron, memory, error calculation circuit) together satisfy the "particular machine" prong of the machine-or-transformation test. Unlike software-implemented neural network patents, no Alice/Mayo step-two analysis is needed here as the claims do not recite a general-purpose computer implementing an abstract process.
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Dependent Claim Fallback Quality
The 12 dependent claims add meaningful technical detail but exhibit structural redundancy that reduces their fallback value. Claims 6–7 and Claims 11–12 are near-parallel pairs adding switching elements with and without memory input routing respectively — their distinction is narrow and could be collapsed under claim differentiation arguments. Claims 8 and 13 both address memory behavior but with slightly different scope (two-information vs. one-information storage), adding genuine fallback. Claims 9–10 (second-embodiment dual-path error signaling) add distinct and valuable fallback positions not captured in Claims 4–5, representing the strongest dependent claim strategy in the set.
⚠️
Abstract Quality
An examiner reading only the abstract would identify the hardware components correctly but would likely misidentify the novel contribution — the abstract describes the system architecture accurately but mentions the GSD/flash device implementation only at the end of a long hardware description, and does not highlight that eliminating Op-Amp/ADC/DAC circuits is the key innovation over the prior art (US 2017/0011290A1). The abstract also omits any reference to the three-phase (forward/backward/weight-update) operational sequence that is central to the on-chip training function, which could lead an examiner to categorise this as a routine hardware neural network improvement rather than a novel training architecture.
✅
Figure Support Quality
Figure support is comprehensive across all 12 drawing sheets (25+ individual figures). Every structural limitation in Claim 1 has direct figure support: cross-bar synapse arrays are shown in FIGs. 3B/3C/4B/4C; the forward neuron capacitor and switching element (Claim 2) map to FIG. 5B/5C; the error calculation circuit maps to FIGs. 7A/7B; the memory layer maps to FIG. 6; the backward neuron differential amplifier and PWM circuit (Claims 4–5) map to FIGs. 9A/9B; the dual-path second-embodiment backward neuron (Claim 9) maps to FIGs. 13A/13B and 14A/14B. No claim element lacks figure support, which is a material strength for §112(a) written description challenges.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
2.8
Prosecution Defensibility
2.5
Spec–Claim Consistency
4.5
Dependent Claim Coverage
3.2
Claim Type Diversity
1.5
Figure Support Quality
4.8
Key observation: Figure Support Quality scores highest (4.8/5.0) because all 25+ individual figures directly map to specific claim limitations across both embodiments, providing exceptional §112(a) written description defense — FIGs. 5B/5C, 7B, 9A/9B, 13B, and 14B in particular provide circuit-level support for every dependent claim limitation. Claim Type Diversity scores lowest (1.5/5.0) because the entire 13-claim set consists exclusively of apparatus claims — the absence of method claims covering the forward/backward propagation and weight update operational sequence, and the absence of CRM claims, creates wide design-around exposure for any competitor who implements the same algorithmic training process using different hardware means. Practitioners reviewing this patent for FTO should note that the method of on-chip neuromorphic training described in the specification (col. 11–14) is entirely unprotected by any claim.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No method claim on training algorithm Single independent claim — total fragility GSD limitation excludes memristor-based designs
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US 12,099,919 B2 — key questions answered
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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