Patent Drafting Analysis of STMicroelectronics’ Convolutional Network MAC Hardware Accelerator | US 11,740,870 B2

IP Drafting Analysis · US 11,740,870 B2

Patent Drafting Analysis of STMicroelectronics' MAC Hardware Accelerator for CNN Inference | US 11,740,870 B2

Q: What does US 11,740,870 B2 protect?

US 11,740,870 B2 protects a Multiply ACcumulate (MAC) hardware accelerator system and method for convolutional neural network inference. The patent specifically claims a digit-serial architecture in which input weights are multiplied by input features by sequentially multiplying individual digits of the weight by the feature, combined with pre-processing logic that gates (clock-disables) the multiplier units when zero-value weight digits are detected, thereby reducing power consumption by avoiding unnecessary computations during the CNN forward pass.

Q: Who owns patent US 11,740,870 B2?

US 11,740,870 B2 is jointly owned by STMICROELECTRONICS S.r.l. (Agrate Brianza, Italy) and STMicroelectronics International N.V. (Geneva, Switzerland). The inventors are Giuseppe Desoli (San Fermo Della Battaglia, Italy), Thomas Boesch (Rovio, Switzerland), Carmine Cappetta (Battipaglia, Italy), and Ugo Maria Iannuzzi (Milan, Italy).

Q: What are the independent claims of US 11,740,870 B2?

Claim 1 is a system claim covering an addressable memory array, processing cores, and an accelerator framework of MAC hardware accelerators with digit-serial weight multiplication and gating pre-processing logic. Claim 7 is a system claim adding the specific limitation of P digit-serial multipliers producing one W-bit by W-bit result per clock cycle. Claim 10 is a system claim covering MAC hardware accelerators performing multiplication via sign-magnitude coding. Claim 12 is a system claim covering individual weight digits stored in a series of memory words. Claim 14 is a mobile computing device claim incorporating an imaging sensor and DCNN processing circuitry with a MAC accelerator framework. Claim 19 is a method claim covering performing MAC operations with digit-serial input multiplication and gating of multipliers using pre-processing logic. Claim 23 is a MAC hardware accelerator apparatus claim covering the plurality of multipliers and output circuitry directly.

Q: What technology does this patent cover?

This patent covers a specialized computer chip design that makes artificial intelligence calculations more energy-efficient. When a neural network processes images or audio, it performs millions of multiply-and-add calculations using learned weight values. Most of these weight values are very close to zero, meaning large portions of each calculation produce no useful result. This patent describes hardware that automatically detects when a weight digit is zero and skips the clock cycle for that calculation, saving the power that would otherwise be wasted on pointless switching activity in the circuit.

Q: What IPC classifications does this patent use?

G06F 7/544 (2006.01) — Arithmetic logic units, adders and related circuits specifically covering multiply-accumulate operations. G06N 3/04 (2023.01) — Computing arrangements based on biological models, specifically neural network architectures and their structural characteristics.

A structural and strategic analysis of US 11,740,870 B2 covering claim architecture, drafting quality signals, dependency coverage, prosecution positioning, and critical gaps in STMicroelectronics' digit-serial multiply-accumulate accelerator patent.

US 11,740,870 B2Filed: Mar 27, 2020Granted: Aug 29, 2023G06F 7/544G06N 3/04

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Spec Words

18,400

Across 6 sections

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Total Claims

6 independent · 22 dependent

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Figure Sheets

Circuit diagrams, timing tables, architecture diagrams

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Published by PatSnap Insights Team · June 3, 2026 · 13 min read Verified by PatSnap Eureka Data

Overview

Structural Overview

The detailed description dominates at approximately 56% of total words, reflecting deep technical exposition across 56 columns covering digit-serial architectures, folding transformations, gating techniques, and sign-magnitude coding. The claim set comprises 28 claims with 6 independent claims spanning system, mobile device, method, and MAC accelerator apparatus types, providing multimodal enforcement coverage. The 50 drawing sheets — among the most extensive in the semiconductor IP class — cover circuit schematics, timing tables, data-flow diagrams, and histograms, providing thorough visual support for the disclosed embodiments.

Section Word Distribution

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Figure Inventory — 50 Sheets

Figure	Description	Role
FIG. 1	Schematic representation of a neural network showing input layer, hidden layers 1 and 2, and output layer connections.Search in Eureka ↗	Other
FIG. 2	Example of ANN operation for image classification showing input image, inference block, and output class probabilities.Search in Eureka ↗	Other
FIG. 3	Embodiment of artificial neuron scheme compared with a biological neuron, showing dendrites, nucleus, axon, and mathematical model.Search in Eureka ↗	Other
FIG. 4	Examples of activation functions including Sigmoid, Hyperbolic Tangent, Rectified Linear Unit (ReLU), and Leaky ReLU.Search in Eureka ↗	Other
FIG. 5	Example connections between neuron 501 of a first convolutional layer and neurons in region 505 and region 507 of the previous layer.Search in Eureka ↗	Other
FIG. 6	Example steps of a convolution computation showing kernel 601 superimposed over input feature map 605 and corresponding output matrix 610.Search in Eureka ↗	Claim support
FIG. 7	Example operation of a convolutional layer with M depth-slices on N input feature maps having C channels, showing input fmaps and filters.Search in Eureka ↗	Other
FIG. 8A	Example of discrete convolution operation with kernel 601 and padded input 805p, illustrating nine computation steps.Search in Eureka ↗	Claim support
FIG. 8B	Enlarged portions of FIG. 8A showing discrete convolution with padded input 805p and kernel 601 positions.Search in Eureka ↗	Claim support
FIG. 8C	Enlarged portions of FIG. 8A showing further discrete convolution steps with kernel 601 and padded input 805p.Search in Eureka ↗	Claim support
FIG. 8D	Enlarged portions of FIG. 8A showing final discrete convolution steps with kernel 601 and padded input 805p.Search in Eureka ↗	Claim support
FIG. 9	Example operation of Max-pooling and Average-pooling layers with 2x2 pooling and stride 2 applied to a 4x4 input matrix.Search in Eureka ↗	Other
FIG. 10	Embodiment of a bit-serial adder architecture showing a full-adder with inputs A0, B0, carry register, TIME signal, and output X0.Search in Eureka ↗	Key embodiment
FIG. 11	Schematic representation of a digit-serial layout cell showing Cap, Bit 0 through Bit N-1, and Control sections.Search in Eureka ↗	Key embodiment
FIG. 12	Graphical representation of example area occupation versus digit size showing predicted and measured relative area curves.Search in Eureka ↗	Other
FIG. 13	Example of throughput versus digit-size for different word sizes (8b, 12b, 16b, 24b) showing sample rate in MHz.Search in Eureka ↗	Other
FIG. 14	Example illustration of area-time product (AT efficiency measure) versus digit-size showing optimal efficiency at small digit sizes.Search in Eureka ↗	Other
FIG. 15	Example scheme of a synchronous system showing combinational logic block M with inputs A, B, C, outputs X, Y, Z, and feedback loops with delay elements.Search in Eureka ↗	Key embodiment
FIG. 16	Example scheme of a circuit obtained using bit-level unfolding transformation showing blocks M(0), M(1), through M(N-1) with combinatorial logic.Search in Eureka ↗	Key embodiment
FIG. 17	Example digit-serial adder circuit with digit-size 3 showing three adder stages with inputs A0/B0, A1/B1, A2/B2 and TIME signal.Search in Eureka ↗	Key embodiment
FIG. 18	Data-flow of a parallel W-bits x W-bits multiplier unit showing digit inputs, parallel multiply stages M0 through MP-1, and digit outputs.Search in Eureka ↗	Key embodiment
FIG. 19	Data-flow of a digit-serial multiplier obtained using folding transformation showing parallel_in, digit_in, parallel x digit block H, and Ldigit_out/Hdigit_out outputs.Search in Eureka ↗	Key embodiment
FIG. 20	Example two's complement computation of -5x5 showing partial product rows and final sum via sign bit extension chain.Search in Eureka ↗	Other
FIG. 21	Example two's complement computation of -5x7 showing partial products with last partial product inversion and carry-in addition.Search in Eureka ↗	Other
FIG. 22	Embodiment of a signed digit-serial multiplier unit with digit-size 2 and word size 4 implemented using carry-save array multiplier architecture with DELAY, summing arrays, PARALLEL/SERIAL and SERIAL/PARALLEL blocks.Search in Eureka ↗	Key embodiment
FIG. 23	Embodiment of a bit-serial multiplier unit with factors of word size 4 bits showing multiply-accumulate chain with delay registers D and coefficient inputs a3, a2, a1, a0.Search in Eureka ↗	Key embodiment
FIG. 24	Embodiment of multiplier unit 2401 having multiple digit-cells 2405, with expanded view of a single digit-cell including partial product generator, carry save array, and digit-to-digit-serial component.Search in Eureka ↗	Key embodiment
FIG. 25	Example embodiment of a bit-serial multiplier unit and digit cell with partial product generator, carry save array, showing inputs B and A with digit cells b3b2b1b0.Search in Eureka ↗	Key embodiment
FIG. 26	Embodiment of a bit-serial multiplier unit and digit cell showing dual partial product generators with inputs A_low and A_up and inputs b3b2b1b0.Search in Eureka ↗	Key embodiment
FIG. 27	Embodiment of data-flow of accumulator unit or circuit showing chained digit_adder stages (digit_adder0 through digit_adderP-1) with carry propagation and digit outputs.Search in Eureka ↗	Key embodiment
FIG. 28	Data-flow of a digit-serial accumulation unit showing digit_adder (H_A) block with digit_in, partial delay (P-delta), and digit_out.Search in Eureka ↗	Key embodiment
FIG. 29	Architecture obtained using word-level unfolding showing input X through P/S converter, Stream 1 through Stream P processing, and S/P converter to output Y.Search in Eureka ↗	Key embodiment
FIG. 30	Embodiment of a digit-serial architecture-based MAC hardware accelerator showing feature input, ds_mult0 through ds_mult(aP-1) multiplier chain, ds_acc0 through ds_acc(aP-1) accumulators, digit-serial converter, and parallel accumulation output.Search in Eureka ↗	Key embodiment
FIG. 31	Example embodiment of an accumulation digit-cell showing N-bit_adder, N-bit_FF_stage (register), c_out flip-flop, and new_acc control signal.Search in Eureka ↗	Key embodiment
FIG. 32	Embodiment of a digit-cell of an example digit-serial accumulation architecture showing adder_i, register_(i+1), and acc_out_(i+1) with carry out flip-flop.Search in Eureka ↗	Key embodiment
FIG. 33	Embodiment of a digit-serial accumulation architecture showing four d_acc_cells (d_acc_cell0 through d_acc_cell3) with mult_out inputs and d_accout/c_out outputs.Search in Eureka ↗	Key embodiment
FIG. 34	Architecture of digit-serial multiplier unit embodiment showing W-bit_FF_stage, digit x parallel multiplier, W-bit_FF_stage (partial sum register), combinatorial digit-shifter, and digit serial output.Search in Eureka ↗	Key embodiment
FIG. 35	Example embodiment of a digit-serial architecture-based MAC hardware accelerator showing feature input, mem. word digit 0-3 multipliers with carry signals, s2p converter, and accumulation output.Search in Eureka ↗	Key embodiment
FIG. 36	Control logic embodiment for generating temp and new_acc control signals for multiplier units 0-3 and accumulators, including a modulus-P counter.Search in Eureka ↗	Flow diagram
FIG. 37	Embodiment of an output converter showing count[1:0] and last signals, four NFF shift register chains, 2:1 multiplexers, and acc_out_lshw output.Search in Eureka ↗	Key embodiment
FIG. 38	Example histograms of trained weights of convolutional layers conv1 through conv5 showing distribution concentrated near zero.Search in Eureka ↗	Claim support
FIG. 39	Embodiment of gating logic showing enable signal generation, gated clock generation block, and gated functional unit with clk input.Search in Eureka ↗	Claim support
FIG. 40	Embodiment of flip-flop based gating logic showing enable signal generation, D flip-flop with OR gate, and en_gclk/gclk outputs to gated functional unit.Search in Eureka ↗	Claim support
FIG. 41A	Embodiment of gating logic showing OR gate combining digit_input_i bits with temp_i, D flip-flop generating en_gclk, AND gate producing gclk for gated multiplier unit.Search in Eureka ↗	Claim support
FIG. 41B	Example schematic timing information for gating logic of FIG. 41A showing clk, mem_out, en, en_gclk, gclk, and mult_in waveforms.Search in Eureka ↗	Claim support
FIG. 42	MAC unit block diagram showing feature input, parallel input, four digit input/sign ports (mem. word digit 0-3 with digit_N[3]), weight input from memory, acc_output, and batch result.Search in Eureka ↗	System architecture
FIG. 43	Embodiment of array multiplier structure showing MB cells arranged with feature sign inputs a0, a1 and partial sum input to generate multiplication results.Search in Eureka ↗	Key embodiment
FIG. 44	Embodiment of a modified carry save array multiplier structure for sign-magnitude multiplication showing MB cells with a0, a1 inputs and b3b2b1b0 digits.Search in Eureka ↗	Key embodiment
FIG. 45	Example histogram of weights of a trained SqueezeNet convolutional layer showing weight values distribution from -0.15 to 0.25.Search in Eureka ↗	Claim support
FIG. 46	Schematic design flow for power consumption estimation showing RTL Verilog, synthesis, gate-level simulation, switching activity annotation, and Synopsys PrimeTime power analysis steps.Search in Eureka ↗	Other
FIG. 47	Reference architecture diagram showing five-pipeline-stage pipelined bit-parallel MAC with WxN multipliers 0-3 (pipe1-pipe4) and accumulation unit (pipe5).Search in Eureka ↗	Other
FIG. 48	Schematic diagram of exemplary electronic processor-based device 4800 including NN accelerator 4801, processor circuitry 4802, memory circuitry 4804, GPU 4812, and various I/O interfaces.Search in Eureka ↗	System architecture
FIG. 49	Embodiment of processor-based device 4900 showing convolution accelerator 4901 operating with SoC 4910 and co-processor subsystem 4915 including dual DSP clusters and global RAM.Search in Eureka ↗	System architecture
FIG. 50	Table 1 timing diagram of digit-serial MAC circuit showing 27 clock cycles of MAC unit 0-3 operations across accumulation sets acc1-acc3 for MACs 1-8.Search in Eureka ↗	Claim support
FIG. 51	Table 2 sequence of operations computed by the cluster multiplier unit showing 15 clock cycles across multiplier units 0-3 for MAC1-MAC4 operations.Search in Eureka ↗	Claim support
FIG. 52	Table 3 example of standard weight memorization strategy for P=4, showing memory locations and digit columns (Digit 3, 2, 1, 0) with weight assignments iw_n.Search in Eureka ↗	Claim support
FIG. 53	Table 4 alternative weight memorization strategy for P=4 digit-serial MAC architecture showing interleaved digit storage across memory words.Search in Eureka ↗	Claim support
FIG. 54	Table 5 example relationship between count[1:0] counter values, accumulation register ports, digit-serial converter assignments (conv1/conv2), and bit-parallel output.Search in Eureka ↗	Claim support
FIG. 55	Table 6 example of trained weights of AlexNet convolutional layers conv1-conv5 showing weights range, 95% occurrences interval, biggest magnitude boundary, and corresponding binary word.Search in Eureka ↗	Claim support
FIG. 56	Table 7 area comparison between described digit-serial MAC architecture (3897 gate count) and reference bit-parallel architecture (3665 gate count).Search in Eureka ↗	Other

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Claims

Claim Architecture Analysis

The patent contains 28 claims with 6 independent claims covering system (Claims 1, 7, 10, 12), mobile computing device (Claim 14), method (Claim 19), and MAC hardware accelerator apparatus (Claim 23) types, providing enforcement coverage across deployment modalities. The 22 dependent claims yield a ratio of 3.67:1, below the semiconductor industry norm of 4-8:1, suggesting some missed fallback opportunities. The multimodal independent claim strategy — spanning system, device, method, and apparatus — is strategically sound, though the lack of an explicit SoC-level claim and the absence of a CRM claim represent notable omissions.

Core inventive concept: The claims address the problem of high power consumption in CNN hardware accelerators by using a digit-serial multiply-accumulate architecture where, per Claim 1, an accelerator framework comprising a plurality of MAC hardware accelerators 'multiplies an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature,' combined with pre-processing logic that 'controls gating of multipliers' to skip clock cycles when zero-value weight digits are detected, thereby exploiting the zero-heavy distribution of trained CNN weights.

Independent Claim Dissection

Claim	Preamble	Transition	Key Body Elements
Claim 1	A system,	comprising:	an addressable memory array; one or more processing cores; an accelerator framework including a plurality of MAC hardware accelerators that multiply input weight digits by input feature sequentially; pre-processing logic controlling gating of multipliers of the MAC hardware acceleratorsSearch prior art ↗
Claim 7	A system,	comprising:	an addressable memory array; one or more processing cores; an accelerator framework including a plurality of MAC hardware accelerators multiplying input weight digits by input feature sequentially; MAC hardware accelerator having P digit-serial multipliers producing one W-bit by W-bit multiplication result per clock cycleSearch prior art ↗
Claim 10	A system,	comprising:	an addressable memory array; one or more processing cores; an accelerator framework including a plurality of MAC hardware accelerators multiplying input weight digits by input feature sequentially; MAC hardware accelerators performing multiplication operations via sign-magnitude codingSearch prior art ↗
Claim 12	A system,	comprising:	an addressable memory array; one or more processing cores; an accelerator framework including a plurality of MAC hardware accelerators multiplying input weight digits by input feature sequentially; individual digits of input weight stored in a series of words of a memory arraySearch prior art ↗
Claim 14	A mobile computing device,	comprising:	an imaging sensor that captures images; processing circuitry implementing a deep convolutional neural network including a memory and an accelerator framework with a plurality of MAC hardware accelerators that multiply input weight digits by input feature sequentiallySearch prior art ↗
Claim 19	A method,	comprising:	performing a plurality of multiply accumulate operations using a plurality of MAC hardware accelerators that multiply a digit-serial input by a parallel input by sequentially multiplying individual digits; generating an output based on results; controlling gating of multipliers using pre-processing logic of the accelerator frameworkSearch prior art ↗
Claim 23	A Multiple Accumulate (MAC) hardware accelerator,	comprising:	a plurality of multipliers multiplying a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input; circuitry coupled to the plurality of multipliers outputting a result based on multiplication of the digit-serial input by the parallel inputSearch prior art ↗

Claim Dependency Tree

1 System: addressable memory array + processing cores + MAC accelerator framework with digit-serial weight multiplication + gating pre-processing logicSearch Claim 1 prior art ↗

2 Adds: pre-processing logic controls gating of MAC multipliersSearch in Eureka ↗

3 Adds: pre-processing logic includes passive selection logic within one or more gating circuitsSearch in Eureka ↗

4 Further (dep. on 3): gating circuit includes OR gate, flip-flop, and AND gate serially coupled to control clock of digit-serial multiplierSearch in Eureka ↗

5 Adds: gating a multiplier comprises detecting zero-value weight digits and gating in responseSearch in Eureka ↗

6 Adds: individual digits of input weight stored in sign and magnitude coding formatSearch in Eureka ↗

7 System: addressable memory + processing cores + MAC accelerator with P digit-serial multipliers producing one W-bit x W-bit result per clock cycleSearch Claim 7 prior art ↗

8 Adds: MAC hardware accelerator comprises accumulation circuitry and timing control circuitry controlling data flow between P digit-serial multipliers and accumulation circuitrySearch in Eureka ↗

9 Further (dep. on 8): accelerator framework controls data flow to plurality of MAC hardware accelerators to synchronize operationSearch in Eureka ↗

10 System: addressable memory + processing cores + MAC accelerator framework performing multiplication operations via sign-magnitude codingSearch Claim 10 prior art ↗

11 Adds: MAC hardware accelerators convert output of at least one multiplication operation to 2's complement prior to accumulation stepSearch in Eureka ↗

12 System: addressable memory + processing cores + MAC accelerator framework with individual digits of input weight stored in series of words of memory arraySearch Claim 12 prior art ↗

13 Adds: a word in the series of words stores digits of a plurality of different input weightsSearch in Eureka ↗

14 Mobile computing device: imaging sensor + processing circuitry implementing DCNN with MAC accelerator framework multiplying input weight digits by input featureSearch Claim 14 prior art ↗

15 Adds: mobile computing device comprises pre-processing logic controlling gating of multipliers of MAC hardware acceleratorsSearch in Eureka ↗

16 Further (dep. on 15): gating a multiplier comprises detecting zero-value weight digits and gating in responseSearch in Eureka ↗

17 Adds: MAC hardware accelerator of the plurality has P digit-serial multipliers producing one W-bit by W-bit multiplication result per clock cycleSearch in Eureka ↗

18 Adds: individual digits of input weight stored in series of words of memorySearch in Eureka ↗

19 Method: performing plurality of MAC operations using MAC hardware accelerators multiplying digit-serial input by parallel input; generating output; gating of multipliers controlled by pre-processing logicSearch Claim 19 prior art ↗

20 Adds: gating a multiplier of a MAC hardware accelerator in response to detecting a zero-value input digitSearch in Eureka ↗

21 Adds: storing individual digits of digit-serial input in a series of words of a memorySearch in Eureka ↗

22 Further (dep. on 21): a word in the series of words stores digits of a plurality of different digit-serial inputsSearch in Eureka ↗

23 MAC hardware accelerator apparatus: plurality of multipliers multiplying digit-serial input by parallel input by sequentially multiplying individual digits; circuitry outputting resultSearch Claim 23 prior art ↗

24 Adds: pre-processing logic controlling gating of the plurality of multipliersSearch in Eureka ↗

25 Further (dep. on 24): pre-processing logic includes OR gate, flip-flop, and AND gate serially coupled to control a clock of a multiplierSearch in Eureka ↗

26 Further (dep. on 24): pre-processing logic detects zero-value digits and gates multiplier in response to zero-value digitSearch in Eureka ↗

27 Adds: plurality of multipliers produce one W-bit by W-bit multiplication result in a clock cycleSearch in Eureka ↗

28 Further (dep. on 27): MAC hardware accelerator comprises accumulation circuitry and timing control circuitry controlling data flow between P digit-serial multipliers and accumulation circuitrySearch in Eureka ↗

Metric	This Application	Semiconductor / AI Hardware Norm
Total claims	28	20 – 30
Independent claim count	6	3 – 6
Dependent : Independent ratio	3.67 : 1	4 – 8 : 1
Method claims present?	Yes — Claim 19	Common
System / apparatus claims?	Yes — Claims 1, 7, 10, 12, 23	Always

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Drafting Quality

Drafting Quality Signals

The patent's greatest strength is the detailed figure support (50 sheets) providing rich written description for the hardware claims, particularly the gating logic in Claims 3-5 which is directly mapped to FIGS. 39-41B. The principal weakness is that the independent claims recite functional language without numeric parameters — for example, Claims 1 and 23 do not recite the digit-size N or word-size W as claim limitations, leaving potential design-around opportunities through minor parameter changes.

✅

Antecedent Basis

The claim set is largely clean with respect to antecedent basis. In Claim 1, "an accelerator framework" is introduced and thereafter referenced as "the accelerator framework" consistently in dependent Claims 2, 5. In Claim 23, "a plurality of multipliers" is introduced and referred back to as "the plurality of multipliers" in Claims 24, 25, 26, maintaining clean antecedent chains. No orphaned "the" references were identified in the independent claims, reducing §112(a) written description challenge risk.

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✅

Spec–Claim Consistency

Independent Claim 1's pre-processing logic limitation maps directly to the gating logic depicted in FIG. 39 (clock gating structure) and FIG. 41A (implemented gating logic with OR gate, flip-flop, AND gate), with detailed written description at columns 47-48. The digit-serial multiplication limitation of Claims 1, 7, 14, 19, and 23 is supported by FIG. 18 (data-flow of parallel W-bits x W-bits multiplier), FIG. 19 (folding transformation), and FIG. 34 (digit-serial multiplier circuit), with corresponding description at columns 27-30. Every independent claim limitation appears to have specific figure and paragraph support.

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✅

Transition Word Usage

All independent claims use "comprising" as the transition, which is the correct open-ended choice for hardware apparatus and system claims in this technology field — it ensures that implementations with additional components such as GPU units, DMA engines, or additional memory arrays are not excluded from the claim scope. The specification at column 7 explicitly states that "comprising" is to be construed in an open, inclusive sense as "including but not limited to," reinforcing prosecutorial consistency. No missed opportunities for "consisting essentially of" variations were identified that would have been strategically valuable here.

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⚠️

§112(f) Means-Plus-Function Risk

The SoC embodiment described in the Summary section at column 4 uses explicit "means for" language — e.g., "means for storing kernel data," "means for processing applications," and "means for performing multiply accumulate operations" — which if recited in claims would invoke §112(f) and require identification of corresponding structure in the specification. These "means for" recitations do not appear in the granted claims (Claims 1-28), so the prosecution risk was successfully avoided in the final claim set. However, the Summary's means-plus language creates a record that examiners or litigants could cite to narrow the scope of functional language in the apparatus claims.

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✅

§101 Eligibility Risk

The §101 exposure for this patent is low because all independent claims are directed to concrete hardware — specifically, a system comprising "an addressable memory array," "one or more processing cores," and an "accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators." These hardware recitations anchor all claims to specific machine elements, directly satisfying the machine-or-transformation test. Claim 19 is the method claim and could face abstract idea challenges, but the limitation that MAC hardware accelerators "multiply a digit-serial input... by sequentially multiplying individual digits" ties the method to hardware operation, providing a strong §101 defense.

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⚠️

Dependent Claim Fallback Quality

The dependent claim landscape is somewhat repetitive across the four parallel system-type independent claims (Claims 1, 7, 10, 12). For example, the zero-value gating limitation appears as Claim 5 (dependent on Claim 1) and again as Claim 16 (dependent on Claim 15 dependent on Claim 14) and Claim 20 (dependent on Claim 19) and Claim 26 (dependent on Claim 24 dependent on Claim 23) — providing good coverage breadth but adding limited unique fallback depth. Claims 8 and 28 provide genuinely distinct value by adding the accumulation circuitry and timing control circuitry limitations, while Claims 6 and 11 provide distinct sign-magnitude and 2's complement conversion fallback positions.

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⚠️

Abstract Quality

The abstract accurately describes the hardware accelerator structure — it mentions the plurality of multipliers, the digit-serial input, the parallel input, and the sequential multiplication of digits — but it omits the zero-value gating mechanism that is the primary novel contribution differentiating this invention from prior digit-serial MAC architectures. An examiner reading only the abstract would identify the invention as a digit-serial MAC accelerator but might not recognize the key power-saving gating innovation as the distinguishing feature over Chang et al. or other cited prior art. The abstract's final sentence does reference gating ("The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits") but does not explicitly recite zero-value detection.

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✅

Figure Support Quality

The 50 drawing sheets provide exceptional figure support for the claim limitations. The gating pre-processing logic of Claims 2-5 is supported by FIGS. 39, 40, 41A, and 41B. The digit-serial multiplication of Claims 1, 7, 14, 19, and 23 is supported by FIGS. 18, 19, 22, 34, and 35. The accumulation circuitry of Claims 8 and 28 is supported by FIGS. 27-33. The sign-magnitude coding of Claim 10 is supported by FIGS. 43 and 44. The memory word storage of Claim 12 is supported by FIGS. 52 (Table 3) and 53 (Table 4). No independent claim limitation was identified without corresponding figure support, which is the strongest quality dimension of this filing.

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Scorecard

Strategic Intent Scorecard

Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.

Claim Breadth

3.5

Prosecution Defensibility

3.8

Spec–Claim Consistency

4.5

Dependent Claim Coverage

3.2

Claim Type Diversity

Figure Support Quality

4.8

Key observation: This patent scores highest on Figure Support Quality (4.8/5) — 50 drawing sheets provide exceptional circuit-level support for every claim limitation including explicit schematics for the gating logic (FIGS. 41A/41B), accumulation architecture (FIGS. 31-33), and timing tables (FIGS. 50-51), making written description challenges difficult to sustain. The lowest dimension is Dependent Claim Coverage (3.2/5) — the 22 dependent claims are distributed across 6 independent claims with significant repetition of the zero-value gating and memory storage limitations rather than adding architecturally distinct fallback positions such as specific digit-size ranges, clock frequency parameters, or specific neural network layer types. Practitioners analyzing this patent for design-around opportunities should focus on the gap between the independent claims' broad functional language and the specific P=4, W=16, N=4 implementation parameters disclosed in the specification but not claimed.

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Critical Gaps

3 Critical Gaps in This Claim Set

A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.

GAP 01 · HIGHEST IMPACT

No CRM / Non-Transitory Storage Medium Claim Filed

The patent contains system claims (Claims 1, 7, 10, 12), a mobile device claim (Claim 14), a method claim (Claim 19), and a hardware accelerator apparatus claim (Claim 23), but conspicuously omits any computer-readable medium or non-transitory storage medium claim covering instructions for configuring or controlling the MAC accelerator framework. This creates an enforcement gap: a competitor that distributes FPGA configuration bitstreams or embedded software libraries implementing the digit-serial gating algorithm without physically manufacturing the hardware accelerator would not directly infringe any granted claim. A stronger filing would have included a CRM claim reciting instructions that, when executed by processing circuitry, cause the system to perform digit-serial MAC operations with zero-value gating, particularly given that the patent explicitly contemplates software-configurable implementations (FIG. 48 shows instructions 4814 in storage 4860).

GAP 02 · HIGH IMPACT

Independent Claims Lack Numeric Parameter Limitations as Prosecution History Defense

All six independent claims recite the digit-serial MAC framework using generic variables ("a plurality of digits," "a plurality of bits") without specifying the digit-size N, word-size W, or the number P of digit-serial multipliers as claim limitations, even though the specification extensively describes optimal parameter values (N=4, W=16, P=W/N=4). While this breadth is initially favorable, it creates a dual risk: during prosecution the examiner may find broad prior art on digit-serial multipliers (Chang et al. 1997 is cited), and competitors can design systems with alternative parameter choices arguing non-infringement based on design differences not captured in the claims. A stronger filing would have included at least one dependent claim per independent claim explicitly reciting W and P as integers greater than 1 with N being a divisor of W, matching the exact language of Claims 7 and 27 but as fallback dependent positions under Claims 1 and 23.

GAP 03 · HIGH IMPACT

Sign-Magnitude Coding Claim Isolated From Gating Claims

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3 Critical Gaps in This Claim Set

See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.

No CRM claim on accelerator control Missing numeric parameter fallback claims Sign-magnitude isolated from gating claims

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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.

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Patent Information

Patent No.US 11,740,870 B2

AssigneeSTMICROELECTRONICS S.r.l. and STMicroelectronics International N.V.

FiledMarch 27, 2020

PublishedAugust 29, 2023

PriorityMarch 29, 2019

App. No.16/833,353

StatusGranted · Active

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MAC accelerator CNN inference patents› STMicroelectronics hardware AI portfolio› Competitive digit-serial multiplier art› Pre-processing gating logic prior art› Edge AI inference chip landscape›

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