Patent Drafting Analysis of Taiwan Semiconductor Manufacturing Company’s Fan-Out Chip Package Structure | US 2024/0203893 A1
Patent Drafting Analysis of TSMC's Fan-Out Chip Package with Interposer Substrate | US 2024/0203893 A1
A structural and strategic analysis of US 2024/0203893 A1 covering claim architecture, drafting quality signals, critical gaps, and prosecution positioning for TSMC's fan-out semiconductor packaging technology.
Spec Words
9,200
Across 5 sections
Draft now ↗
Total Claims
20
3 independent · 17 dependent
Draft now ↗
Figure Sheets
41
Package cross-sections, process stages, embodiment variants
Draft now ↗
Published by PatSnap Insights Team · · 12 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description overwhelmingly dominates at approximately 72% of total specification words (~7,200 of ~9,200 words), spread across 41 drawing sheets depicting numerous cross-sectional process stages. The patent presents 20 total claims — 3 independent and 17 dependent — yielding a 5.67:1 dependent-to-independent ratio, which sits at the lower end for semiconductor packaging IPC classes that typically see broader dependent claim sets. Figure coverage is extensive with 41 sheets spanning eight distinct embodiment families (FIGS. 1A–1G, 2, 3A–3H, 4A–4F, 5A–5F, 6A–6D, 7A–7G, 8A–8G, and 9), providing strong visual support for nearly every structural element recited in the claims.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 41 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1A | Cross-sectional view showing initial process stage with redistribution structure 102 formed over carrier substrate 100, including insulating layers 104, conductive features 106, and conductive pillars 112.Search in Eureka ↗ | Key embodiment |
| FIG. 1B | Cross-section showing semiconductor die 114 stacked over redistribution structure 102, bonded via conductive features 116 and underfill material 118, with device elements 120 including electrodes 121a and 121b.Search in Eureka ↗ | Key embodiment |
| FIG. 1C | Cross-section showing interposer substrate 122 (comprising board 124 and conductive elements 126) stacked over redistribution structure 102 and bonded via conductive structures 128, with device element 130 added.Search in Eureka ↗ | Key embodiment |
| FIG. 1D | Cross-section showing device elements 132 disposed over interposer substrate 122 and interconnection structure 136 with redistribution structure 132 added, illustrating the fan-out feature assembly.Search in Eureka ↗ | Key embodiment |
| FIG. 1E | Cross-section showing module 134 carried by interconnection structure 136 stacked over interposer substrate 122, bonded via solder elements 142 to conductive pillars 112.Search in Eureka ↗ | Claim support |
| FIG. 1F | Cross-section showing formation of protective layer 144 surrounding semiconductor die 114, interposer substrate 122, device elements 132, conductive pillars 112 and solder elements 142.Search in Eureka ↗ | Claim support |
| FIG. 1G | Cross-section of completed package structure showing second semiconductor die 148 stacked over redistribution structure 102 with conductive features 150 and underfill 152, plus conductive bumps 146.Search in Eureka ↗ | Key embodiment |
| FIG. 2 | Cross-sectional view of package structure variant where semiconductor die 148 is not bonded onto redistribution structure 102, showing conductive bumps 146 on the bottom surface.Search in Eureka ↗ | Key embodiment |
| FIG. 3A | Cross-section showing alternative process embodiment with conductive pillars 112' formed over redistribution structure 102 on carrier substrate 100, no die yet placed.Search in Eureka ↗ | Claim support |
| FIG. 3B | Cross-section showing semiconductor die 302 bonded via conductive features 304 and underfill 306, device elements 308 placed on redistribution structure 102, with alternative carrier substrate 112'.Search in Eureka ↗ | Claim support |
| FIG. 3C | Cross-section showing interposer substrate 310 (board 314, conductive elements 312) stacked over redistribution structure 102 and bonded via conductive structures 316, with protective layer 318 formed.Search in Eureka ↗ | Key embodiment |
| FIG. 3D | Cross-section showing protective layer 318 formation surrounding semiconductor die 302, device elements 308, conductive pillars 112' and conductive structures 316 on interposer substrate 310.Search in Eureka ↗ | Claim support |
| FIG. 3E | Cross-section showing carrier substrate 320 bonded to interposer substrate 310 and subsequent removal of original carrier substrate 100 to expose redistribution structure 102 surface.Search in Eureka ↗ | Flow diagram |
| FIG. 3F | Cross-section showing conductive bumps 322, additional semiconductor die 324 and second die package structure bonded via conductive features 326 and underfill 328 onto exposed redistribution structure 102.Search in Eureka ↗ | Key embodiment |
| FIG. 3G | Cross-section showing removal of carrier substrate 320 to expose interposer substrate 310 surface, with semiconductor die 330 and device elements 336 then disposed over interposer substrate 310.Search in Eureka ↗ | Flow diagram |
| FIG. 3H | Cross-section of completed package structure after singulation, showing semiconductor die 330 and device elements 336 on interposer substrate 310, with second semiconductor die 324 on opposite side.Search in Eureka ↗ | Key embodiment |
| FIG. 4A | Cross-section showing redistribution structure 102 formed over carrier substrate 101 with release film 101, initial stage for an alternative fan-out package process flow.Search in Eureka ↗ | Flow diagram |
| FIG. 4B | Cross-section showing semiconductor die 402 bonded via conductive features 404, underfill 406 formed, and device elements 408 placed over redistribution structure 102 with release film 101.Search in Eureka ↗ | Claim support |
| FIG. 4C | Cross-section showing module 416 on interconnection structure 410 stacked over redistribution structure 102, bonded via conductive structures 418, with protective layer 420 formed surrounding all elements.Search in Eureka ↗ | Key embodiment |
| FIG. 4D | Cross-section showing package structure flipped and attached to tape carrier 422, with carrier substrate 100 and release film 101 removed to expose redistribution structure 102.Search in Eureka ↗ | Flow diagram |
| FIG. 4E | Cross-section showing conductive bumps 424 formed over exposed redistribution structure 102 surface, and second semiconductor die 426 bonded via conductive features 428 and underfill 430.Search in Eureka ↗ | Key embodiment |
| FIG. 4F | Cross-section of singulated, completed package structure after tape carrier 422 removal, showing the full fan-out package with dies on both sides of redistribution structure 102.Search in Eureka ↗ | Key embodiment |
| FIG. 5A | Cross-section showing alternative embodiment start with redistribution structure 102 on carrier substrate 101 and a second redistribution structure substrate 502 prepared separately.Search in Eureka ↗ | Flow diagram |
| FIG. 5B | Cross-section showing semiconductor die 503 attached via adhesive element 506 (die attach tape) to redistribution structure substrate 502 with conductive pillars 504 facing upward and protective layer 508 formed.Search in Eureka ↗ | Claim support |
| FIG. 5C | Cross-section showing second redistribution structure 510 (insulating layers 512, conductive features 514, conductive elements 516 and 518) formed over protective layer 508 with protective layer 516 added.Search in Eureka ↗ | Key embodiment |
| FIG. 5D | Cross-section showing semiconductor die 520 bonded via conductive features 522, underfill 524, device elements 526 placed, and interconnection structure 528 with module 534 stacked over redistribution structure 510.Search in Eureka ↗ | Key embodiment |
| FIG. 5E | Cross-section showing protective layer 538 formed surrounding semiconductor die 520, device elements 526, interconnection structure 528 and conductive structures 536 over redistribution structure 510.Search in Eureka ↗ | Claim support |
| FIG. 5F | Cross-section of completed package structure after carrier substrate 100 and release film 101 removal with conductive bumps 540 formed, showing the singulated fan-out package with double redistribution layers.Search in Eureka ↗ | Key embodiment |
| FIG. 6A | Cross-section showing similar structure to FIG. 5D provided or received, as a starting point for yet another package process embodiment series with redistribution structure 510 and substrate 502.Search in Eureka ↗ | Flow diagram |
| FIG. 6B | Cross-section showing interposer substrate 602 (board 604, conductive elements 606) stacked over redistribution structure 510, bonded via conductive structures 608, with protective layer 610 formed.Search in Eureka ↗ | Key embodiment |
| FIG. 6C | Cross-section showing module 618 on interconnection structure 612 stacked over interposer substrate 602 via conductive structures 620, underfill 622 formed, and conductive bumps 624 added after carrier removal.Search in Eureka ↗ | Key embodiment |
| FIG. 6D | Cross-section of singulated completed package structure from the FIG. 6 series, showing fan-out package with interposer, two redistribution layers, and conductive bumps 624 on the bottom.Search in Eureka ↗ | Key embodiment |
| FIG. 7A | Cross-section showing redistribution structure 102 on carrier substrate 101 with semiconductor die 702 and device element 708 stacked over it, initiating a further process embodiment series.Search in Eureka ↗ | Flow diagram |
| FIG. 7B | Cross-section showing interposer substrate 710 (board 712, conductive elements 714, protective dielectric layer 718) stacked over redistribution structure 102 via conductive structures 716, with protective layer 718 formed.Search in Eureka ↗ | Key embodiment |
| FIG. 7C | Cross-section showing package flipped and attached to carrier substrate 720 via release film 722, with carrier substrate 100 and release film 101 removed to expose redistribution structure 102 bottom.Search in Eureka ↗ | Flow diagram |
| FIG. 7D | Cross-section showing conductive pillars 724 formed over redistribution structure 102, semiconductor die 726 bonded via conductive features 728, with second die protective layer 730 formed.Search in Eureka ↗ | Key embodiment |
| FIG. 7E | Cross-section showing redistribution structure 732 (insulating layers 734, conductive features 736) formed over protective layer 730 after planarization, with conductive bumps 738 to be formed.Search in Eureka ↗ | Claim support |
| FIG. 7F | Cross-section showing conductive bumps 738 formed over redistribution structure 732, and module 748 on interconnection structure 742 attached to interposer substrate 710 via conductive structures 750, underfill 752.Search in Eureka ↗ | Key embodiment |
| FIG. 7G | Cross-section of singulated completed package after tape carrier 740 removal, showing the full multi-die fan-out package with redistribution structures on both sides and interposer substrate 710 with module 748.Search in Eureka ↗ | Key embodiment |
| FIG. 8A | Cross-section showing redistribution structure 102 formed over carrier substrate 101 with release film 101, initial stage for the FIG. 8 process series using pre-bonded interposer substrate 802.Search in Eureka ↗ | Flow diagram |
| FIG. 8B | Cross-section showing interposer substrate 802 (board 804, conductive elements 806) stacked over redistribution structure 102 via conductive structures 814, with semiconductor die 808 pre-bonded to interposer substrate 802 via conductive features 810 and underfill 812.Search in Eureka ↗ | Key embodiment |
| FIG. 8C | Cross-section showing conductive pillars 820 formed over interposer substrate 802, semiconductor die 822 bonded via conductive features 826 on interposer substrate 802, with device element 830 disposed and protective layer 816 present.Search in Eureka ↗ | Key embodiment |
| FIG. 8D | Cross-section showing protective layer 832 formed surrounding semiconductor die 822, device element 830 and conductive pillars 820 over interposer substrate 802, with planarization applied.Search in Eureka ↗ | Claim support |
| FIG. 8E | Cross-section showing redistribution structure 834 (insulating layers 836, conductive features 838) formed over protective layer 832, with module 846 on interconnection structure 840 stacked and bonded via conductive structures 848, underfill 850.Search in Eureka ↗ | Key embodiment |
| FIG. 8F | Cross-section showing package after removal of carrier substrate 100 and release film 101, with second redistribution structure visible and interconnection structure 840 with module 846 at top, and conductive elements 844, 842 labeled.Search in Eureka ↗ | Flow diagram |
| FIG. 8G | Cross-section of singulated completed FIG. 8 series package structure showing the full multi-die fan-out package with conductive bumps 852 on redistribution structure 102 bottom surface.Search in Eureka ↗ | Key embodiment |
| FIG. 9 | Enlarged cross-sectional view near device element 120 showing electrodes 121a' and 121b' with C-shape profile bonded to pad regions 902a and 902b in redistribution structure 102, with underfill element 904 protecting joints.Search in Eureka ↗ | Claim support |
Analysis powered by PatSnap Eureka. Patent text and figures publicly available from USPTO. Draft a Similar Patent
Claims
Claim Architecture Analysis
The patent presents 3 independent claims: Claim 1 (apparatus — package structure), Claim 8 (apparatus — package structure with alternative configuration), and Claim 15 (method — forming a package structure). The 17 dependent claims across 3 independent claims yield a 5.67:1 ratio, below the typical semiconductor packaging norm of 6–10:1, suggesting room for broader fallback claim layers. The dual apparatus/method structure ensures enforcement coverage across both product and process infringement theories, though the absence of a computer-readable medium or system-level claim leaves some infringement vectors open.
Core inventive concept: The claims solve the problem of signal transmission inefficiency and large package footprint in multi-die semiconductor assemblies by interposing a second semiconductor die that "partially overlaps the first semiconductor die in a direction perpendicular to a surface of the redistribution structure" — a specific geometric relationship creating a vertical fan-out — while a "first protective layer surrounding the first semiconductor die" provides mechanical encapsulation. Claims 1 and 8 express this spatial overlap arrangement from different structural perspectives (redistribution-side-up vs. interposer-side-up), while Claim 15 expresses the same concept as a process requiring the projection of one die to cover part of the other over the dielectric layer.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A package structure, comprising: | comprising | a redistribution structure; an interposer substrate disposed over the redistribution structure; a first semiconductor die disposed between the redistribution structure and the interposer substrate; a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface of the redistribution structure; a first protective layer surrounding the first semiconductor dieSearch prior art ↗ |
| Claim 8 | A package structure, comprising: | comprising | an interposer substrate; a first semiconductor die; a first protective layer surrounding the first semiconductor die and in contact with the interposer substrate; a second semiconductor die overlapping the first semiconductor die and separated from the first protective layer; a first conductive structure disposed on the first semiconductor die; a first underfill material, wherein the first protective layer and the first conductive structure are separated by the first underfill materialSearch prior art ↗ |
| Claim 15 | A method for forming a package structure, comprising: | comprising | forming conductive features in a dielectric material layer; disposing a first semiconductor die on a first side of the dielectric material layer; disposing a second semiconductor die on a second side of the dielectric material layer, wherein a projection of the first semiconductor die over the dielectric material layer covers a part of a projection of the second semiconductor die over the dielectric material layer; forming a first protective layer in contact with the first semiconductor dieSearch prior art ↗ |
Claim Dependency Tree
1 Package structure: redistribution structure + interposer substrate + first die between them + second die partially overlapping first die + first protective layerSearch Claim 1 prior art ↗
2 Adds: first protective layer extends between the first semiconductor die and the interposer substrateSearch in Eureka ↗
3 Adds: second protective layer surrounding the second semiconductor dieSearch in Eureka ↗
4 Further (dep. on 3): first protective layer and second protective layer are separated by the interposer substrateSearch in Eureka ↗
5 Adds: first protective layer is in contact with a sidewall of the interposer substrateSearch in Eureka ↗
6 Adds: adhesive element disposed between the first semiconductor die and the redistribution structureSearch in Eureka ↗
7 Adds: the second semiconductor die is exposed from the package structureSearch in Eureka ↗
8 Package structure: interposer substrate + first semiconductor die + first protective layer in contact with interposer + second die overlapping first die separated from first protective layer + first conductive structure + first underfill materialSearch Claim 8 prior art ↗
9 Adds: first protective layer covers a surface of the first semiconductor die facing away from the interposer substrateSearch in Eureka ↗
10 Adds: projection of first semiconductor die over interposer substrate extends over a projection of the second semiconductor die over the interposer substrateSearch in Eureka ↗
11 Further (dep. on 10): adds a third semiconductor die, wherein projection of third die over interposer extends over projection of second die over interposer and projection of second die over interposerSearch in Eureka ↗
12 Further (dep. on 11): second semiconductor die and the third semiconductor die are exposed from the package structureSearch in Eureka ↗
13 Adds: second conductive structure on second semiconductor die and second protective layer surrounding second semiconductor die in contact with second conductive structureSearch in Eureka ↗
14 Adds: first dielectric material layer + first conductive feature in it + second dielectric material layer + second conductive feature in it, wherein interposer substrate is sandwiched by both layersSearch in Eureka ↗
15 Method: forming conductive features in dielectric layer; disposing first die on first side; disposing second die on second side with overlapping projections; forming first protective layer in contact with first dieSearch Claim 15 prior art ↗
16 Adds: forming a second protective layer extending between the second semiconductor die and the dielectric material layerSearch in Eureka ↗
17 Further (dep. on 16): forming a conductive structure in the second protective layer, wherein height of second semiconductor die is less than height of conductive structureSearch in Eureka ↗
18 Further (dep. on 16): forming a conductive structure between the second semiconductor die and the dielectric material layer and in contact with the second protective layerSearch in Eureka ↗
19 Adds: the dielectric material layer is surrounded by the first protective layerSearch in Eureka ↗
20 Adds: forming first conductive structure on first side with height greater than first die; forming second conductive structure on second side with height greater than second dieSearch in Eureka ↗
| Metric | This Application | Semiconductor Packaging Norm |
|---|---|---|
| Total claims | 20 | 15 – 30 |
| Independent claim count | 3 | 2 – 4 |
| Dependent : Independent ratio | 5.67 : 1 | 6 – 10 : 1 |
| Method claims present? | Yes — Claim 15 | Common |
| System / apparatus claims? | Yes — Claims 1, 8 | Always |
Analysis powered by PatSnap Eureka. Patent text and figures publicly available from USPTO. Draft a Similar Patent
Drafting Quality
Drafting Quality Signals
The patent demonstrates strong structural clarity in Claims 1 and 8, with each independent claim reciting well-defined geometric relationships — the partial overlap limitation in Claim 1 and the underfill separation limitation in Claim 8 — that directly distinguish over prior packaging structures. However, the relatively thin dependent claim set (only 17 dependent claims across 3 independent claims) and the absence of material composition claims for the protective layer or conductive features creates unnecessary prosecution vulnerability if the geometric claim elements face anticipation rejections.
✅
Antecedent Basis
Antecedent basis is consistently maintained throughout the claim set. In Claim 1, "the redistribution structure," "the interposer substrate," "the first semiconductor die," and "the second semiconductor die" each have proper antecedents introduced in the preamble or earlier claim body. In Claims 8 and 15, all "the" references similarly trace back to elements introduced in the same claim. Dependent claims 2–14 reference elements introduced in parent Claims 1 or 8 correctly, and the "second protective layer" in Claim 3 is properly introduced before being referenced in Claim 4.
✅
Spec–Claim Consistency
The specification provides robust support for all independent claim limitations. The "redistribution structure" of Claim 1 is directly supported by FIGS. 1A–1G and paragraphs [0021]–[0029]. The "interposer substrate disposed over the redistribution structure" maps to FIG. 1C and paragraph [0034]. The critical "second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface" is supported by FIGS. 1G and 3F–3H showing dies on opposite sides with the described spatial relationship, reinforced by paragraph [0152]–[0153]. The method claim's "projection of the first semiconductor die covers a part of a projection of the second semiconductor die" is directly described in paragraph [0155].
✅
Transition Word Usage
All three independent claims and all dependent claims correctly use "comprising" as the transition word, which is the strategically optimal choice for this technology domain — it creates open-ended claims that cannot be avoided merely by adding additional components. The use of "comprising" in method Claim 15 similarly preserves broad coverage over manufacturing processes that include the recited steps plus additional steps. No narrowing transitions such as "consisting of" or "consisting essentially of" appear anywhere in the claim set, which is appropriate given TSMC's enforcement objectives in semiconductor packaging.
✅
§112(f) Means-Plus-Function Risk
No "means for" or "step for" language appears in any of the 20 claims, avoiding mandatory §112(f) interpretation. All structural elements are recited as concrete nouns — "redistribution structure," "interposer substrate," "semiconductor die," "protective layer," "conductive structure," "underfill material" — with no purely functional claim elements lacking structural definition. The one potential concern is the term "dielectric material layer" in Claims 15–20, which is defined functionally in the method context, but the specification at paragraph [0023] provides adequate structural support through specific material examples including PBO, polyimide, and epoxy-based resin.
✅
§101 Eligibility Risk
This patent carries minimal §101 eligibility risk because all claims are directed to concrete physical structures (apparatus claims 1 and 8) or physical manufacturing processes (method claim 15) — not abstract ideas, laws of nature, or natural phenomena. The patent falls squarely within the USPTO's eligible subject matter category of "manufacture" and "process" for semiconductor device fabrication. The Alice/Mayo two-step analysis is clearly satisfied: the claims are not directed to an abstract idea but to specific structural configurations of semiconductor dies, interposer substrates, redistribution structures, and protective layers with defined spatial relationships.
⚠️
Dependent Claim Fallback Quality
Several dependent claims add meaningful distinctions — Claim 6 (adhesive element between first die and redistribution structure), Claim 14 (double dielectric layer sandwich of interposer substrate), and Claims 17–18 (conductive structure height relationship) each provide distinct structural fallback positions. However, Claims 7 and 12 ("exposed from the package structure") are cosmetic limitations adding minimal prosecution value; an examiner could argue the exposure condition is inherent in the base structure. Claims 11–12 (third semiconductor die) provide genuine multidie hierarchy coverage but could benefit from explicit pitch and spacing language to further distinguish over stacked die art.
⚠️
Abstract Quality
The abstract accurately describes the structural components — "redistribution structure, an interposer substrate disposed over the redistribution structure, a first semiconductor die disposed between the redistribution structure and the interposer substrate, a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface" — but fails to articulate the technical problem solved or the specific advantage of the partial overlap geometry (reduced signal transmission delay and smaller footprint). An examiner reading only the abstract might classify this as a conventional stacked-die package rather than recognizing the novel spatial overlap feature that distinguishes it from prior art. Paragraph [0152] in the specification better captures the improvement: "The RC delay and/or signal noise are significantly reduced."
✅
Figure Support Quality
Figure support is exceptional, with 41 drawing sheets providing cross-sectional views at every key process stage across 8 distinct embodiment families. Every structural limitation in Claims 1 and 8 — redistribution structure, interposer substrate, first and second semiconductor dies, protective layer, conductive structures, and underfill material — is illustrated in at least FIGS. 1A–1G and the corresponding detailed description paragraphs [0021]–[0055]. The partial overlap relationship critical to Claim 1 is depicted in FIG. 1G and FIGS. 3F–3H. The method claim limitations of Claim 15 are covered by FIGS. 1A–1G, 3A–3H, and 4A–4F process sequences. FIG. 9 provides an enlarged view of the electrode C-shape profile detail for device element 120, supporting the dependent claim structures.
Analysis powered by PatSnap Eureka. Patent text and figures publicly available from USPTO. Draft a Similar Patent
Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
3.5
Prosecution Defensibility
3.8
Spec–Claim Consistency
4.5
Dependent Claim Coverage
3.2
Claim Type Diversity
3.5
Figure Support Quality
4.8
Key observation: Figure Support Quality scores highest (4.8/5.0) because the 41 drawing sheets provide comprehensive cross-sectional coverage of every structural element and process step across 8 independent embodiment families, making written description rejections under §112(a) highly unlikely. Dependent Claim Coverage scores lowest (3.2/5.0) because Claims 7 and 12 add only superficial "exposed from the package" limitations that provide minimal prosecution fallback value, and the set lacks material composition claims for the protective layer — the most commercially sensitive element — which would have been added in a stronger filing as dependent claims specifying molding compound material, filler content, and CTE matching properties. Practitioners reviewing this patent should note that the absence of CRM/system-level claims and the thin dependent claim strategy around the protective layer material creates a clear continuation opportunity.
See how your own draft compares — Open Eureka IP Drafting →
Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
🔒
3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No protective layer material claims Overlap geometry undefined in claims Missing system-level module claims
Unlock Full Analysis — Free Frequently asked questions
US 2024/0203893 A1 — key questions answered
Still have questions? PatSnap Eureka can answer them from patent data instantly. Search in Eureka
Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
Ask anything about this patent.
PatSnap Eureka searches patents and data to answer instantly.
PatSnap Eureka searches patents and data to answer instantly.
Powered by PatSnap Eureka
Link copied to clipboard