In a terse but consequential per curiam ruling issued on July 16, 2024, the U.S. Court of Appeals for the Federal Circuit affirmed the unpatentability of U.S. Patent No. 7,126,214 B2, owned by Arbor Global Strategies, LLC, in its dispute against semiconductor giant Xilinx, Inc. The panel — comprising Circuit Judges Hughes, Linn, and Stark — issued a Rule 36 affirmance, upholding the lower tribunal’s invalidity or cancellation determination without additional written opinion. The patent at issue covers a reconfigurable processor module comprising hybrid stacked integrated circuit die elements, a technology with direct relevance to modern FPGA and heterogeneous computing architectures.

This ruling carries significant strategic weight for IP professionals and R&D teams operating in the semiconductor and reconfigurable computing space. A Rule 36 affirmance signals that the Federal Circuit found no reversible error worthy of extended analysis, effectively cementing the unpatentability finding as precedent. For patent holders asserting stacked die and hybrid chip architecture claims, and for companies like Xilinx defending against such assertions, this outcome underscores the critical importance of robust prior art searches and prosecution-stage claim differentiation in complex integrated circuit technology domains.

Case Overview

The Parties

The Patent at Issue

U.S. Patent No. 7,126,214 B2 (application number US10/802067) covers a reconfigurable processor module that uses hybrid stacked integrated circuit die elements — essentially a multi-chip module architecture where different types of processor dies are physically stacked and electrically interconnected to form a reconfigurable computing unit. The key claims relate to the structural and functional integration of heterogeneous die elements within a single package to achieve reprogrammable processing capabilities. This technology is directly applicable to advanced FPGA platforms, system-in-package (SiP) designs, and high-performance computing architectures where flexibility and density are paramount.

• • US7126214B2

Legal Representation

Plaintiff Counsel: Kramer Levin Naftalis & Frankel, LLP (lead: James R. Hannah)
Defendant Counsel: Fish & Richardson LLP (lead: David M. Hoffman)

Litigation Timeline & Procedural History

Case No. 22-1549 was filed before the U.S. Court of Appeals for the Federal Circuit — the exclusive appellate venue for patent matters in the United States — on March 21, 2022, placing it squarely within the Federal Circuit’s specialized jurisdiction over patent validity and invalidity disputes. This appeal-level proceeding, arising from the District of Columbia region, involved a patentability verdict cause categorized as an Invalidity/Cancellation Action, suggesting the underlying dispute was resolved at a lower tribunal such as the Patent Trial and Appeal Board (PTAB) before reaching the Federal Circuit on appeal.

The case ran for 848 days from filing to closure on July 16, 2024 — a duration consistent with a fully briefed Federal Circuit appeal that proceeded through standard examination without expedited treatment. Resolution came via a per curiam Rule 36 judgment, meaning the Federal Circuit affirmed the lower tribunal’s unpatentability finding without issuing a written opinion, a procedural mechanism used when the court finds no novel legal question requiring elaboration. This basis of termination — unpatentable — conclusively extinguished the patent claims at issue, with no damages, injunctive relief, or remand recorded in the public record.

The Verdict & Legal Analysis

Outcome

The U.S. Court of Appeals for the Federal Circuit issued a per curiam affirmance under Federal Circuit Rule 36 on July 16, 2024, upholding the determination that U.S. Patent No. 7,126,214 B2 is unpatentable. The basis of termination is recorded as ‘Unpatentable,’ meaning the patent’s claims were found invalid and will not be enforceable. No damages award, injunctive relief, or cost allocation was disclosed in the public record, as the proceeding terminated on patentability grounds rather than infringement liability.

Verdict Cause Analysis

The verdict cause — Patentability, classified as an Invalidity/Cancellation Action — points to a substantive challenge to the patent’s validity, most likely grounded in prior art or obviousness arguments prosecuted through an inter partes review or similar PTAB proceeding.

• The Federal Circuit’s Rule 36 affirmance indicates the panel found no reversible legal error in the lower tribunal’s unpatentability determination, lending strong finality to the invalidity finding against US7126214B2.
• An Invalidity/Cancellation Action of this type typically involves challenges under 35 U.S.C. §§ 102 or 103, meaning the claims covering the reconfigurable processor module were likely found anticipated by or obvious over prior art in the stacked integrated circuit or reconfigurable computing field.
• The per curiam nature of the ruling, with no dissent noted among Judges Hughes, Linn, and Stark, suggests the appellate panel was unanimous in finding the lower tribunal’s validity analysis sound and unremarkable from a legal standpoint.
• Because the case is categorized as an appeal originating from the District of Columbia region and involving a cancellation action, the underlying proceeding was most likely a PTAB inter partes review (IPR) or covered business method (CBM) proceeding, with Xilinx as petitioner challenging the patent before the Board.

Legal Significance

1. A Rule 36 affirmance by the Federal Circuit in a patent cancellation proceeding carries full precedential weight as a final judgment on patentability, meaning US7126214B2’s claims are definitively extinguished and cannot be reasserted against Xilinx or any other party.
2. This outcome reinforces the Federal Circuit’s consistent deference to PTAB unpatentability findings when the record reflects a thorough prior art analysis, signaling to patent holders in the semiconductor and reconfigurable computing space that claims lacking robust differentiation from existing art face serious vulnerability on IPR appeal.
3. For pending patent applications and continuation strategies in the hybrid stacked die and reconfigurable processor module space, this ruling highlights that claim drafters must construct limitations that are clearly distinguishable from the prior art landscape that was sufficient to invalidate the ‘214 patent, as the Federal Circuit has signaled it will not disturb well-supported Board determinations.

Strategic Takeaways

For Patent Attorneys:

• When prosecuting continuation or divisional applications in the reconfigurable processor and stacked die space, draft claims with structural limitations that go materially beyond the functional language found in US7126214B2 to withstand IPR scrutiny and Federal Circuit review.
• A Federal Circuit Rule 36 affirmance forecloses further appeal to the Supreme Court on the merits in most practical scenarios — advise patent assertion clients holding related family members to conduct an immediate family portfolio audit for vulnerability to similar invalidity challenges.
• In preparing IPR petitions against semiconductor architecture patents, the Federal Circuit’s silent affirmance in this case signals receptivity to prior art arguments targeting hybrid stacked IC claims — prioritize documentary prior art from the early 2000s chip packaging literature when constructing obviousness combinations.

For IP Professionals:

• In-house IP teams at FPGA, SiP, and adaptive computing companies should monitor the invalidated claims of US7126214B2 and cross-reference against any pending assertions from related patent families held by Arbor Global Strategies to assess whether those portfolios face similar prior art exposure.
• Use this outcome as a trigger to audit your company’s own stacked die and reconfigurable processor patent portfolio for claims that mirror the structural and functional language of the invalidated ‘214 patent, and consider proactive claim amendment or continuation filings to strengthen differentiation.

For R&D Teams:

• R&D teams developing hybrid stacked IC architectures, multi-die FPGAs, or reconfigurable computing modules can note that the ‘214 patent’s claims have been extinguished, removing one assertion risk — however, teams should conduct a broader FTO analysis to identify surviving related patents in this crowded technology space.
• Engineering teams working on next-generation system-in-package or chiplet designs should document design choices and contemporaneous prior art references during development to build a defensible record against future invalidity or infringement claims in the stacked die domain.