In a decisive ruling issued on July 16, 2024, the U.S. Court of Appeals for the Federal Circuit affirmed the invalidation of U.S. Patent No. 7,282,951 B2, held by Arbor Global Strategies, LLC, in its dispute against programmable logic giant Xilinx, Inc. The case, filed on March 21, 2022 and resolved after 848 days of proceedings, centered on a reconfigurable processor module comprising hybrid stacked integrated circuit die elements — a technology directly relevant to high-performance FPGA and advanced packaging architectures. The Federal Circuit issued its affirmance under Rule 36, upholding the lower tribunal’s finding of unpatentability without a written opinion.

This outcome carries significant weight for IP professionals navigating the crowded semiconductor and reconfigurable computing landscape. The Rule 36 affirmance signals judicial confidence in the unpatentability finding, creating immediate implications for patent portfolios covering hybrid stacked IC and reconfigurable processor technologies. Patent attorneys, in-house IP teams, and R&D leaders in FPGA, chiplet, and advanced packaging fields should closely examine how this ruling reshapes freedom-to-operate risk, prosecution strategy, and portfolio valuation in one of the semiconductor industry’s most contested technology domains.

Case Overview

The Parties

The Patent at Issue

U.S. Patent No. 7,282,951 B2 (application number US11/383,149) covers a reconfigurable processor module that combines multiple types of integrated circuit die stacked together in a hybrid configuration — a design intended to enable flexible, high-performance computing by linking programmable logic with other processor elements in a single compact package. The patent’s key claims relate to the structural and functional arrangement of these stacked hybrid die elements, making it relevant to modern chiplet architectures, heterogeneous integration, and advanced FPGA packaging. Real-world applications include high-density computing modules used in data centers, defense electronics, and AI acceleration hardware.

• • US7282951B2

Legal Representation

Plaintiff Counsel: Kramer Levin Naftalis & Frankel, LLP (lead: James R. Hannah)
Defendant Counsel: Fish & Richardson LLP (lead: David M. Hoffman)

Litigation Timeline & Procedural History

This appeal was heard by the U.S. Court of Appeals for the Federal Circuit, the specialized appellate court with exclusive jurisdiction over U.S. patent matters, sitting in the District of Columbia. The case reached the Federal Circuit as an appeal from a patentability/invalidity determination — meaning the substantive question of whether US7282951B2 met the statutory requirements for patent protection had already been adjudicated at a lower tribunal (likely the Patent Trial and Appeal Board or a district court), and Arbor Global sought reversal of that unpatentability finding. The Federal Circuit’s role at this appellate level was to review legal conclusions de novo and factual findings for clear error, making its affirmance a high-bar confirmation of the lower body’s reasoning.

The case spanned 848 days from filing on March 21, 2022 to closure on July 16, 2024 — a duration consistent with the typical timeline for Federal Circuit patent appeals, which often involve extensive briefing schedules, amicus participation, and oral argument preparation. The matter was resolved by a Rule 36 judgment of affirmance, meaning the Federal Circuit found the lower tribunal’s decision sufficiently well-reasoned that no additional written opinion was necessary. The basis of termination was recorded as ‘Unpatentable,’ confirming that US7282951B2 was stripped of patent protection following the completed appellate review. No settlement, damages award, or injunctive relief was recorded in the public case record.

The Verdict & Legal Analysis

Outcome

The Federal Circuit issued a Rule 36 affirmance on July 16, 2024, upholding the underlying finding that U.S. Patent No. 7,282,951 B2 is unpatentable, resulting in the cancellation of the asserted patent claims. No damages award or injunctive relief was entered, as the proceeding turned solely on the question of patent validity rather than infringement. Specific cost allocation details were not disclosed in the publicly available case record for this appellate proceeding.

Verdict Cause Analysis

The Federal Circuit’s affirmance rested on the verdict cause of patentability — specifically, an invalidity or cancellation action challenging whether US7282951B2 satisfied the statutory requirements for patent protection.

• The core legal question was whether U.S. Patent No. 7,282,951 B2, directed to a reconfigurable processor module with hybrid stacked integrated circuit die elements, met the requirements of patentability under 35 U.S.C. §§ 102 and/or 103 in light of prior art in the semiconductor and stacked IC field.
• The lower tribunal determined that the challenged claims were unpatentable — a finding the Federal Circuit affirmed in full under Rule 36, signaling that the appellate judges found no reversible legal error or clearly erroneous factual finding in the invalidity determination.
• A Rule 36 affirmance without written opinion indicates the Federal Circuit concluded the lower tribunal’s reasoning was sufficiently thorough and correct on the law to require no further elaboration, lending strong institutional weight to the unpatentability conclusion.
• The basis of termination recorded as ‘Unpatentable’ confirms that the patent claims at issue were cancelled or invalidated as a result of this proceeding, extinguishing Arbor Global’s ability to assert those claims against Xilinx or any other party going forward.

Legal Significance

1. The Federal Circuit’s Rule 36 affirmance, while non-precedential in the formal sense, carries practical weight as a signal that the prior art and legal arguments marshaled against US7282951B2 were compelling enough to withstand appellate scrutiny — establishing a strong reference point for challengers of related hybrid stacked IC patents.
2. This outcome reinforces the vulnerability of broad reconfigurable processor and hybrid stacked die patents to invalidity challenges, particularly as the FPGA and chiplet technology space has accumulated substantial prior art through decades of academic research, DARPA programs, and industry filings.
3. Patent owners in the advanced packaging and heterogeneous integration space should note that the invalidation of US7282951B2 may affect claim scope and prosecution strategy for related continuation or divisional applications, as examiners and PTAB panels may cite this outcome when evaluating similar claim language.

Strategic Takeaways

For Patent Attorneys:

• When prosecuting patents on hybrid stacked IC or reconfigurable processor architectures, draft claims with specificity that distinguishes over the crowded prior art landscape that proved fatal to US7282951B2 — generic functional language for stacked die arrangements is particularly vulnerable.
• The Rule 36 affirmance in this case suggests the PTAB or district court’s claim construction and prior art analysis were airtight; attorneys defending similar patents should invest heavily in pre-trial claim differentiation arguments and secondary consideration evidence.
• Consider proactively auditing continuation and related family applications stemming from the same priority chain as US7282951B2 (application US11/383,149), as the invalidity finding may create prosecution estoppel or disclaimer arguments that limit claim scope in surviving family members.

For IP Professionals:

• In-house IP teams at semiconductor and FPGA companies should flag US7282951B2 and its invalidation in their freedom-to-operate databases, updating FTO clearance opinions for reconfigurable processor and hybrid stacked IC products accordingly.
• Portfolio managers holding patents with claim language similar to US7282951B2 — particularly those directed to hybrid die stacking or reconfigurable processor modules — should assess whether those assets remain licensable or defensible in light of this Federal Circuit affirmance.

For R&D Teams:

• R&D teams developing next-generation chiplet, 2.5D/3D IC, or reconfigurable processing architectures can take note that the invalidation of US7282951B2 potentially clears a patent obstacle in this design space, but should still conduct updated FTO searches given the breadth of the remaining patent landscape.
• Engineering teams should document technical distinctions between their hybrid stacked IC implementations and the now-invalidated claims of US7282951B2 to support design-freedom arguments and to inform future patent application drafting around genuinely novel aspects of their architectures.