Bell Semiconductor v. Ambarella: Dismissed With Prejudice After 503 Days
Bell Semiconductor, LLC asserted two semiconductor design patents — US7007259B2 and US6436807B1 — against Ambarella, Inc., targeting the CV25MA0 device and EDA tool workflows for dummy metal insertion and interconnect layout. The case resolved by joint stipulation with plaintiff’s claims dismissed with prejudice and each party bearing its own costs, closing after 503 days in the Ohio Northern District Court.
Semiconductor IP assertion ends in finality — but only for plaintiff
Filed on 23 September 2022 in the Ohio Northern District Court, Bell Semiconductor, LLC brought an infringement action against Ambarella, Inc. asserting two semiconductor process patents: US7007259B2, directed to interconnect layer layout methods, and US6436807B1, directed to dummy metal insertion in circuit designs. The accused products included Ambarella’s CV25MA0-RH A1919 device and the use of Cadence, Synopsys, and Siemens EDA tools to implement dummy metal and interconnect workflows.
The case closed on 8 February 2024 via a Joint Stipulation of Dismissal, with the court ordering all of plaintiff Bell Semiconductor’s claims dismissed with prejudice. Notably, Ambarella’s counterclaims and defenses were dismissed without prejudice, preserving the defendant’s ability to revive those positions in future proceedings. Each party was ordered to bear its own costs, expenses, and attorneys’ fees — a mutual cost structure consistent with a negotiated resolution rather than adjudicated defeat.
The 503-day duration before dismissal suggests substantive engagement occurred before the parties reached their agreed exit. The asymmetric dismissal structure — plaintiff’s claims out with prejudice, defendant’s counterclaims out without prejudice — is commercially significant: Bell Semiconductor cannot re-litigate these specific claims against Ambarella, while Ambarella retains optionality. The public record does not disclose whether a confidential settlement agreement underpins the stipulation.
Filing to Case Dismissed in 503 days
503 days — longer than the median U.S. patent case dismissal, suggesting negotiation preceded settlement
Asymmetric dismissal: what the with/without prejudice split means for both parties
Joint stipulation dismissal: a consensual but binding exit
A Joint Stipulation of Dismissal reflects mutual agreement between the parties to end litigation, but the court’s order governs finality. Here, plaintiff’s claims were dismissed with prejudice — a res judicata bar preventing Bell Semiconductor from re-asserting these patents on these claims against Ambarella. Defendant’s counterclaims were dismissed without prejudice, meaning Ambarella’s positions were not adjudicated on the merits and remain available.
Rule 41 stipulated dismissalWith prejudice vs. without: the asymmetry that defines finality
Dismissal with prejudice is a final judgment on the merits for res judicata purposes — Bell Semiconductor is permanently barred from asserting these same patent claims against Ambarella in future U.S. litigation. Dismissal without prejudice for Ambarella’s counterclaims means those defenses and challenges — potentially including invalidity arguments against US7007259B2 and US6436807B1 — were not resolved and could theoretically be raised again in a different proceeding.
Res judicata bars re-filingBell Semiconductor permanently barred from re-asserting these claims
The with-prejudice dismissal is the most consequential outcome for Bell Semiconductor as a patent licensing entity. It cannot re-file the same infringement claims against Ambarella on US7007259B2 or US6436807B1. The equal cost-bearing order suggests no monetary recovery was publicly documented. Whether a confidential licence or lump-sum payment was part of the resolution is not disclosed in the public record.
No further assertion against AmbarellaAmbarella retains counterclaim optionality — a meaningful asymmetry
Ambarella’s counterclaims and defenses — which in patent infringement actions typically include invalidity and non-infringement — were dismissed without prejudice. This preserves Ambarella’s ability to challenge the asserted patents in future contexts, including IPR petitions at the USPTO. Combined with the mutual cost order, Ambarella exits this litigation without an adverse merits finding and with strategic flexibility intact.
Invalidity challenges preservedFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Bell Semiconductor, LLC | Company | Semiconductor IP licensing entity — holder of US7007259B2 and US6436807B1Search in Eureka ↗ |
| Defendant | Ambarella, Inc. | Company | Ambarella, Inc. — fabless semiconductor company specialising in video and AI SoC designSearch in Eureka ↗ |
| Plaintiff counsel | Kathryn Elizabeth Yukevich | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Richard Eric Gaum | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | William David Ellerman | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | McKool Smith PC | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Taft Stettinus & Hollister, LLP | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Tillotson Johnson & Patton | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Defendant counsel | Aaron T. Brogdon | Attorney | Counsel for Ambarella, Inc.Search in Eureka ↗ |
| Defendant law firm | Frost, Brown & Todd LLC | Law Firm | Representing Ambarella, Inc.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Ohio Northern District CourtSearch in Eureka ↗ |
Official order — verbatim text
The court’s order closely mirrors the parties’ joint stipulation language, granting dismissal on agreed terms without independent merits analysis. The operative asymmetry — plaintiff’s claims out with prejudice, defendant’s counterclaims out without prejudice — is legally significant: it reflects a bargained allocation of finality. Bell Semiconductor accepts a permanent bar on these claims; Ambarella preserves all defensive positions. The mutual cost order further suggests neither party secured a clearly superior litigation outcome, consistent with a negotiated resolution.
US7007259B2 & US6436807B1 — Semiconductor interconnect layout and dummy metal insertion
US7007259B2 (application no. US10/632622) covers methods for making a layout for an interconnect layer of a semiconductor device — a core back-end-of-line (BEOL) design step in integrated circuit fabrication. US6436807B1 (application no. US09/484310) addresses the insertion of dummy metal fills into circuit designs, a technique used to achieve planarisation uniformity during chemical mechanical polishing. Both patents cover fundamental steps in the EDA-assisted physical design flow used by virtually all advanced fabless semiconductor companies.
The strategic relevance of these patents lies in their targeting of EDA tool-mediated workflows: the complaint named Cadence, Synopsys, and Siemens tools as the instruments through which infringement allegedly occurred. This positions the patents as broadly applicable to standard industry practice, creating risk for any fabless SoC vendor using these tools for interconnect or fill processing. Bell Semiconductor’s assertion against Ambarella’s CV25MA0 device illustrates how legacy process patents can be deployed against modern AI-vision SoC architectures that rely on the same foundational physical design steps.
Should your design team run an FTO against US7007259B2 and US6436807B1?
Any fabless semiconductor company — or EDA tool user — running automated interconnect layout generation or dummy metal fill insertion as part of a standard BEOL physical design flow should treat these patents as active FTO risk. The explicit naming of Cadence, Synopsys, and Siemens tool outputs in the complaint means the infringement theory does not require bespoke design choices; standard EDA-driven workflows may be sufficient to trigger claim analysis. Companies shipping SoCs with advanced node layouts are most exposed.
PatSnap Eureka’s FTO Search Agent allows R&D and IP teams to map claims of US7007259B2 and US6436807B1 against current design flow documentation in minutes. Eureka can identify claim scope, locate prior art that may support invalidity arguments, and flag related Bell Semiconductor portfolio patents that could form the basis of future assertions — enabling proactive risk mitigation before a demand letter arrives.
Run a freedom-to-operate analysis on US7007259B2 to assess your product’s exposure
Run FTO in Eureka →Similar semiconductor IP infringement cases in U.S. district courts
Cases involving semiconductor process and EDA-assisted design patents in U.S. district courts — comparable Bell Semiconductor assertions and fabless SoC defendant profiles.
What this case signals for the semiconductor EDA and IP licensing landscape
Asymmetric dismissal structures in NPE-vs-fabless cases carry licensing and portfolio signals worth tracking.
With-prejudice dismissal is a hard stop for Bell Semiconductor’s Ambarella claims
Bell Semiconductor, as a licensing-focused entity, has foreclosed any future assertion of US7007259B2 and US6436807B1 against Ambarella. For competitors and EDA tool vendors watching NPE activity, this signals the assertion against Ambarella is resolved — but Bell’s portfolio may still be active against other fabless SoC companies using similar interconnect and dummy metal workflows.
EDA tool workflows are now explicitly in NPE crosshairs
The complaint specifically named Cadence, Synopsys, and Siemens tool use as the infringing activity pathway — meaning the theory of liability ran through EDA-facilitated semiconductor design steps. IP teams at fabless companies using these tools for interconnect layout or dummy metal insertion should assess whether their design flows create exposure under similar semiconductor process patents still in Bell Semiconductor’s portfolio.
Bell v Ambarella — key questions answered
The case was dismissed by joint stipulation on 8 February 2024. Bell Semiconductor’s claims were dismissed with prejudice, permanently barring re-assertion against Ambarella. Ambarella’s counterclaims and defenses were dismissed without prejudice. Each party bore its own costs and attorneys’ fees. No merits judgment was issued.
Bell Semiconductor asserted US7007259B2, covering methods for interconnect layer layout in semiconductor devices, and US6436807B1, covering dummy metal insertion into circuit designs. Both patents target standard back-end-of-line physical design steps typically performed using EDA tools from Cadence, Synopsys, or Siemens.
The accused products included Ambarella’s CV25MA0-RH A1919 device and the use of Cadence, Synopsys, and/or Siemens EDA tools to insert dummy metal into circuit designs and to make layouts for interconnect layers of semiconductor devices. The infringement theory thus extended to EDA-facilitated design workflows, not solely a single chip.
Dismissal with prejudice operates as a final judgment on the merits for res judicata purposes. Bell Semiconductor is permanently barred from reasserting US7007259B2 and US6436807B1 against Ambarella in U.S. federal court. However, the patents remain enforceable against third parties, and Bell Semiconductor may continue asserting them against other companies in separate proceedings.
This asymmetric structure is typical of negotiated patent dismissals. Plaintiff Bell Semiconductor accepted with-prejudice finality to achieve closure, while Ambarella preserved its counterclaim positions — likely invalidity and non-infringement defenses — without prejudice. This allows Ambarella to potentially challenge the patents via USPTO inter partes review or in future litigation if circumstances change, without those claims having been adjudicated against it.
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