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Bell Semiconductor v. AMS Sensors USA et al. | Patent Lawsuit 4:23-cv-00069

Bell Semiconductor, LLC v. AMS Sensors USA, Inc. et al.

4:23-cv-00069 E.D. Tex. Closed 2 patents
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Infringement action filed 25 Jan 2023 in the United States District Court for the Eastern District of Texas and closed 7 Dec 2023, with 2 patents asserted. Recorded basis of termination: dismissed with prejudice.

Case recordPatsnap Litigation Data·

Case record

Patents involved
US7231626B2US7396760B2
Case no.
4:23-cv-00069
Verdict cause
Infringement action
Court
E.D. Tex.
Court level
District Court
Case region
Texas
Chief judge
Amos L. Mazzant
Trial level
First instance
Filed – Closed
25 Jan 2023 – 7 Dec 2023
Duration
316 days
Basis of termination
Dismissed with Prejudice
Products & marks
Method and system for reducing inter-layer capacitance in integrated circuits · Method of implementing an engineering change order in an integrated circuit design by windows
Source: Patsnap Litigation Data. Case 4:23-cv-00069, United States District Court for the Eastern District of Texas. Open this record in Eureka
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Patent at issue
US7231626B2 Inactive App. US11/015123

Method of implementing an engineering change order in an integrated circuit design by windows

A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Read claims and description in Eureka
Patent standing
Legal status
Inactive
Granted
12 Jun 2007
Est. expiry
26 Jul 2025
Validity challenges
None recorded
Licences recorded
None recorded
Classification
G06F17/50
Prosecution counsel
MENDELSOHN DUNLEAVY, P.C.
Examiner
KIK, PHALLAKA
US7231626B2 patent drawing, figure 1
Fig. 1
US7231626B2 patent drawing, figure 2
Fig. 2
US7396760B2 Inactive App. US10/991107

Method and system for reducing inter-layer capacitance in integrated circuits

The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Read claims and description in Eureka
Patent standing
Legal status
Inactive
Granted
8 Jul 2008
Est. expiry
10 Dec 2025
Validity challenges
None recorded
Licences recorded
None recorded
Classification
H01L21/4763
Prosecution counsel
MENDELSOHN DUNLEAVY, P.C.
Examiner
PICARDAT, KEVIN M
US7396760B2 patent drawing, figure 1
Fig. 1
US7396760B2 patent drawing, figure 2
Fig. 2
Source: Patsnap patent data + case record. Bibliographic fields and drawings reproduced from the published patent document. Break down the claims
Parties & counsel

Parties of record

Counsel of record

Source: case record + Patsnap company data. Attorney names appear as recorded in the docket. Compare both portfolios
Outcome

Basis of termination

From the record · verbatim

“Plaintiff, pursuant to Fed. R. Civ. P. 41(a)(1), requests this Court to dismiss Plaintiff’s claims for relief against Defendants with prejudice.”

Case 4:23-cv-00069 · E.D. Tex. · closed 7 December 2023
Source: case record, verbatim. The quoted paragraph is the basis-of-termination text as filed.

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Three questions this record usually leads to. Each one runs against the full litigation and patent corpus, and cites what it finds.

FAQ

Frequently asked questions

What is case 4:23-cv-00069?

4:23-cv-00069 is a patent infringement action brought by Bell Semiconductor, LLC against AMS Sensors USA, Inc., filed on 25 Jan 2023 in the United States District Court for the Eastern District of Texas. The case closed on 7 December 2023.

Which patents were asserted in 4:23-cv-00069?

US7231626B2 (“Method of implementing an engineering change order in an integrated circuit design by windows”), assigned to BELL SEMICONDUCTOR, LLC, currently inactive; US7396760B2 (“Method and system for reducing inter-layer capacitance in integrated circuits”), assigned to BELL SEMICONDUCTOR, LLC, currently inactive. The record also lists Method and system for reducing inter-layer capacitance in integrated circuits and Method of implementing an engineering change order in an integrated circuit design by windows.

How was case 4:23-cv-00069 terminated?

The recorded basis of termination is dismissed with prejudice. The termination text reads: “Plaintiff, pursuant to Fed. R. Civ. P. 41(a)(1), requests this Court to dismiss Plaintiff’s claims for relief against Defendants with prejudice.”

What does dismissal with prejudice mean?

A dismissal with prejudice permanently ends the claims that were filed, so the same claims cannot be brought again against that defendant. It is the usual form when the parties have settled.

How long did case 4:23-cv-00069 take?

316 calendar days, from filing on 25 Jan 2023 to closure on 7 December 2023.

Who were the attorneys and the judge in 4:23-cv-00069?

Chief Judge Amos L. Mazzant presided. Ashley N. Moore, Casey Shomaker and Clifford Chad Henson are recorded as counsel for plaintiff Bell Semiconductor. Dipu A. Doshi, Domingo Manuel Llagostera and James G. Gorman III appear for defendant AMS Sensors USA.

Answers reproduce fields from the case record for 4:23-cv-00069 and do not constitute legal advice. Ask your own question

Disclaimer. This page reproduces publicly available court docket data for case 4:23-cv-00069 and is provided for general information and reference only. It is not legal advice and must not be relied upon as such.

Docket data has limits. Records are drawn from a snapshot and may lag the live docket. Sealed filings, amended complaints, counterclaims and post-closure motions may not be reflected. Party names, attorney names and firm affiliations are reproduced as recorded and may contain omissions. Where a field is absent from the record, this page marks it as not recorded rather than inferring a value.

No characterisation of the parties or the outcome. This page reports what the record contains. Nothing here should be read as an assertion that any party infringed, that any patent is valid or invalid, that any settlement occurred, or that any party prevailed.

No FTO or validity opinion. Nothing on this page constitutes a freedom-to-operate, novelty, validity or infringement opinion. Any decision touching a live patent dispute should be verified independently and reviewed with qualified patent counsel.

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