Bell Semiconductor v. Fortinet: Semiconductor Patent Dispute Ends in Prejudicial Dismissal
What would you like to do next?
Choose your path based on your current needs:
📋 Case Summary
| Case Name | Bell Semiconductor, LLC v. Fortinet, Inc. |
| Case Number | 4:23-cv-00978 (E.D. Tex.) |
| Court | Eastern District of Texas, Presided by Chief Judge Sean D. Jordan |
| Duration | Oct 2023 – Apr 2024 5 months 8 days |
| Outcome | Stipulated Dismissal |
| Patents at Issue | |
| Accused Products | Fortinet FortiSOC3 and FortiASIC-CP9 |
Case Overview
The Parties
⚖️ Plaintiff
A patent assertion entity with a portfolio tracing lineage to semiconductor intellectual property developed under the Bell Labs and Agere Systems lineage.
🛡️ Defendant
A global cybersecurity company known for its FortiGate firewall products and custom application-specific integrated circuits (ASICs).
The Patents at Issue
This case involved three U.S. patents covering semiconductor device structures, integrated circuit fabrication processes, and chip architecture. All three patents fall within the broader domain of **semiconductor device patent litigation**.
- • US 7,345,245 — Directed to semiconductor device structures
- • US 8,288,269 — Covering integrated circuit fabrication processes
- • US 8,049,340 — Relating to semiconductor chip architecture
Designing a similar product?
Check if your semiconductor design might infringe these or related patents before launch.
The Verdict & Legal Analysis
Outcome
The case terminated via stipulated dismissal under Fed. R. Civ. P. 41(a)(1)(A)(ii), entered by agreement of both parties. This resolution included a bifurcated prejudice framework, meaning the dismissal was with prejudice for the specific FortiSOC3 and FortiASIC-CP9 products identified in the complaint, and without prejudice for all other Fortinet products not specifically enumerated.
Key Legal Issues
The dismissal’s asymmetric prejudice structure is legally significant. By limiting the with-prejudice bar to specifically identified model numbers, Bell Semiconductor preserved theoretical assertion rights against other Fortinet products, while Fortinet secured definitive closure for its two named chip families, eliminating future liability exposure on those specific model numbers under the three asserted patents. This approach reflects a deliberate pleading and settlement strategy in multi-product patent disputes.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor device design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation.
- View all 47 related patents in this technology space
- See which companies are most active in semiconductor patents
- Understand claim construction patterns
🔍 Check My Product’s Risk
Run a comprehensive FTO analysis for your own technology or product.
- Input your product description or technical features
- AI identifies potentially blocking patents
- Get actionable risk assessment report
High Risk Area
Custom ASIC development in cybersecurity
47 Related Patents
In semiconductor tech space
Design-Around Options
Available for most claims
✅ Key Takeaways
The bifurcated with/without-prejudice dismissal structure preserves plaintiff optionality while providing defendant closure on named products.
Search related case law →Eastern District of Texas continues to attract semiconductor patent assertions with efficient resolution timelines.
Explore precedents →Frequently Asked Questions
Three U.S. patents were asserted: US7,345,245B2, US8,288,269B2, and US8,049,340B2, all covering semiconductor device and integrated circuit technology.
The parties filed a stipulated dismissal under Fed. R. Civ. P. 41(a)(1)(A)(ii), with prejudice as to the FortiSOC3 and FortiASIC-CP9 products specifically named in the complaint, and without prejudice otherwise.
The bifurcated dismissal framework illustrates how product-specific complaint pleading shapes settlement structures, offering a tactical model for both patent holders and defendants in multi-product semiconductor disputes.
Ready to Strengthen Your Patent Strategy?
Join 18,000+ IP professionals using PatSnap Eureka to conduct prior art searches, draft patents, and analyse competitive landscapes with AI-powered precision.
References
- PACER — Federal Court Records
- USPTO Patent Full-Text Database
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.