Bell Semiconductor v. NXP USA — Six-Patent EDA Appeal Voluntarily Dismissed
Bell Semiconductor, LLC brought a Federal Circuit appeal against NXP USA, Inc. asserting six US semiconductor design patents against NXP’s use of Cadence, Synopsys, and Siemens EDA tools. The parties jointly stipulated to voluntary dismissal under FRAP 42(b) after just 77 days, each side bearing its own costs.
Six EDA patents, one swift Federal Circuit exit
Bell Semiconductor, LLC — a patent assertion entity holding a portfolio of semiconductor design and EDA-related patents — appealed to the Court of Appeals for the Federal Circuit against NXP USA, Inc. on 17 October 2023. The case, docketed as 24-1057, centred on six issued US patents (US7007259B2, US7231626B2, US7149989B2, US7396760B2, US7260803B2, and US6436807B1) asserted against NXP’s use of industry-standard EDA design tools from Cadence, Synopsys, and Siemens.
The appeal closed on 2 January 2024 — just 77 days after filing — when the parties filed a joint stipulation of voluntary dismissal under Federal Rule of Appellate Procedure 42(b). The Federal Circuit lifted the stay that had been in place and dismissed the appeal, ordering each side to bear its own costs. The public record does not specify whether the dismissal was with or without prejudice at the appellate level.
A 77-day appellate lifespan is notably brief even by Federal Circuit standards, and the joint nature of the stipulation suggests the parties reached some form of resolution or strategic agreement outside the public record. Whether underlying district-court proceedings remain ongoing, were separately resolved, or were mooted is not disclosed in the appellate order. The absence of a cost award to either side is consistent with a negotiated exit rather than a contested ruling.
Filing to resolution in 77 days
77 days — faster than the vast majority of Federal Circuit patent appeals
What the voluntary dismissal under FRAP 42(b) means for both parties
FRAP 42(b): Joint Stipulation of Voluntary Dismissal
Federal Rule of Appellate Procedure 42(b) allows parties to voluntarily dismiss an appeal by filing a signed agreement. Unlike unilateral withdrawal, a joint stipulation signals mutual consent — both Bell Semiconductor and NXP USA agreed to end the appellate proceedings. The court accepted the stipulation and lifted an existing stay, formally closing the Federal Circuit docket.
Mutual consent dismissalWith or without prejudice? The public record is silent.
A voluntary dismissal can be with prejudice (permanently barring re-assertion of the same claims) or without prejudice (leaving the door open to refile). The Federal Circuit order in this case does not specify either. This ambiguity is common in jointly stipulated dismissals where terms are privately negotiated. Practitioners should not assume finality on the merits without reviewing any underlying district-court docket or private settlement agreement.
Prejudice status unspecifiedEach Party Bears Its Own Costs — No Fee-Shifting
The Federal Circuit ordered that the parties bear their own appellate costs. In contested patent appeals, costs (including certain filing and printing expenses) can be shifted to the losing party. A mutual bear-own-costs order here is consistent with a negotiated resolution and avoids either side claiming a cost ‘win’. It does not speak to attorneys’ fees, which are governed separately under 35 U.S.C. § 285.
No cost shift awardedA Stay Was Lifted — Suggesting Prior Proceedings Were on Hold
The dismissal order notes that a stay was in place before being lifted. This suggests related proceedings — likely at the district-court level — had been stayed pending the Federal Circuit appeal. The lifting of the stay upon dismissal may allow those underlying proceedings to resume, though the public appellate record does not confirm their current status. Parties monitoring NXP’s EDA patent exposure should check district-court dockets for related Bell Semiconductor actions.
Underlying stay liftedFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Bell Semiconductor, LLC | Company | Patent assertion entity — holder of US7007259B2 and five further EDA-related semiconductor design patentsSearch in Eureka ↗ |
| Defendant | NXP USA, Inc. | Company | NXP USA, Inc. — US subsidiary of NXP Semiconductors, a leading global semiconductor manufacturerSearch in Eureka ↗ |
| Plaintiff counsel | Paul Richter Jr. | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Defendant counsel | Barrington E. Dyer | Attorney | Counsel for NXP USA, Inc.Search in Eureka ↗ |
| Defendant counsel | Krista Schwartz | Attorney | Counsel for NXP USA, Inc.Search in Eureka ↗ |
| Presiding judge | Judge / | Chief Judge | Court of Appeals for the Federal Circuit — Chief JudgeSearch in Eureka ↗ |
Stipulation of dismissal — official text
The Federal Circuit’s order is tightly procedural: it lifts a pre-existing stay and records the joint agreement to dismiss under FRAP 42(b), with each party absorbing its own costs. The order makes no findings on the merits of the underlying infringement claims, the validity of any of the six asserted patents, or the scope of NXP’s alleged use of EDA tools. This is a clean appellate exit — neither party can point to this order as a substantive win or loss on the patent questions.
US7007259B2 and five further EDA design-method patents
The six patents asserted in this case — US7007259B2, US7231626B2, US7149989B2, US7396760B2, US7260803B2, and US6436807B1 — form a cluster of US grants covering semiconductor design methodology, consistent with EDA-related process and tool-interaction claims. Application numbers trace to filings across 2003–2004 (with US6436807B1 originating from a 2000 filing), suggesting a coordinated prosecution campaign built around a core inventive concept in chip design workflows.
Bell Semiconductor’s assertion of these patents against NXP’s use of Cadence, Synopsys, and Siemens EDA platforms reflects a strategy of targeting method claims that read on design-tool usage rather than the tools themselves. This approach shifts liability from the EDA vendors to their customers — a significant risk vector for any semiconductor company, fabless designer, or IP group that relies on commercial EDA suites without having conducted FTO analysis against method-patent portfolios held by assertion entities.
Should your EDA workflow be assessed against this six-patent cluster?
Any semiconductor company, fabless design house, or integrated device manufacturer using Cadence, Synopsys, or Siemens EDA tools should consider whether their design workflows could read on method claims in Bell Semiconductor’s portfolio. This case demonstrates that standard EDA tool usage — not custom implementation — is sufficient to attract an infringement assertion. R&D and IP teams approving new design flows or expanding EDA platform use should treat this cluster as a priority FTO review target.
PatSnap Eureka’s FTO Search Agent can map the claims of all six asserted patents against your design process documentation and flag specific method-claim limitations that may require design-around or licensing attention. Claim monitoring alerts can also track any continuation or divisional applications stemming from these patent families — ensuring your team is not surprised by newly issued claims that extend the same inventive concept into your current workflows.
Run a freedom-to-operate analysis on US7007259B2 to assess your product’s exposure
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What this case signals for the EDA and semiconductor IP landscape
Six asserted EDA patents, a Federal Circuit appeal resolved in 77 days — here is what practitioners and product teams should take away.
EDA tool usage creates patent exposure for semiconductor companies
Bell Semiconductor’s theory — asserting design-method patents against NXP’s use of third-party EDA tools from Cadence, Synopsys, and Siemens — illustrates that downstream tool users, not just tool vendors, can face infringement claims. Semiconductor companies relying on standard EDA platforms should audit their workflows against method-claim patents in this space.
Rapid joint dismissals at the Federal Circuit often signal off-record settlement
A 77-day Federal Circuit lifespan ending in a joint stipulation, with no cost award and a lifted stay, is a strong indicator of a privately negotiated resolution. While the terms remain confidential, the pattern is consistent with a licensing agreement or covenant not to sue — outcomes that frequently follow assertion campaigns by patent monetisation entities.
Bell v NXP — key questions answered
Bell Semiconductor asserted six US patents: US7007259B2, US7231626B2, US7149989B2, US7396760B2, US7260803B2, and US6436807B1. All relate to semiconductor design methodology and were asserted against NXP’s use of EDA design tools from Cadence, Synopsys, and Siemens.
FRAP 42(b) allows parties to dismiss an appeal by joint stipulation. In this case, both parties agreed to end the Federal Circuit appeal. The order lifted an existing stay and directed each side to bear its own costs. The public record does not specify whether the dismissal was with or without prejudice.
The Federal Circuit’s dismissal order references lifting a pre-existing stay, suggesting related proceedings — likely at the district-court level — had been paused pending the appeal outcome. The specific basis for the stay is not detailed in the publicly available appellate order.
No. A joint voluntary dismissal under FRAP 42(b) carries no merits determination. The Federal Circuit made no findings on infringement, patent validity, or claim scope. Neither party can rely on this order as a substantive legal victory. The underlying dispute may have been resolved through private agreement.
The case record identifies Cadence, Synopsys, and Siemens design tools as the products through which NXP USA allegedly practised the asserted patents. This is significant because it frames the infringement theory around end-user tool usage rather than the EDA vendors’ own products.
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