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Bell Semiconductor v. Skyworks Solutions — IC Design Patent Dispute | PatSnap
Patent Litigation

Bell Semiconductor v. Skyworks Solutions: IC Design Patents Dismissed Without Prejudice

Bell Semiconductor alleged infringement of two integrated circuit design patents against Skyworks Solutions in Massachusetts. The case was dismissed without prejudice after 195 days, with the court administratively closing proceedings pending an ITC Investigation.

Resolution time
195days
195 days — resolved before any merits ruling, consistent with early-stage dismissal
Patents asserted
2
US7149989B2 and US7260803B2 — dummy metal insertion and IC design validation methods
Outcome
Case Dismissed
Without prejudice — plaintiff may refile; case administratively closed pending ITC proceedings
Cost ruling
Not recorded
No costs or fees ruling recorded in the available docket.
Published by PatSnap Insights Team · Verified by PatSnap Eureka Data
Case overview

IC design patents meet early dismissal as ITC proceedings take centre stage

Bell Semiconductor, LLC filed suit against Skyworks Solutions, Inc. on 26 August 2022 in the United States District Court for the District of Massachusetts (Case No. 1:22-cv-11390), presided over by Judge Allison D. Burroughs. The action asserted two patents — US7149989B2, covering incremental dummy metal insertions in integrated circuit layouts, and US7260803B2, covering methods of early physical design validation and identification of metal short circuits in IC design.

The case was dismissed without prejudice on 9 March 2023. The court's order granted the plaintiff leave to file a motion for an amended complaint within 30 days, required the defendant to respond within 14 days of any such motion, and directed that the case be administratively closed pending the conclusion of a parallel ITC Investigation. The recorded Basis of Termination is 'Case Dismissed'; the docket order specifically styles the dismissal as without prejudice with administrative closure tied to ITC proceedings.

The 195-day duration and the court's administrative closure instruction suggest that parallel proceedings before the International Trade Commission were a material factor in the district court's decision to stand down. Whether Bell Semiconductor ultimately filed an amended complaint or allowed the matter to lapse is not disclosed in the available record.

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Case at a glance
CourtMassachusetts District Court
JudgeAllison D. Burroughs
FiledAugust 26, 2022
ClosedMarch 9, 2023
Duration195 days
OutcomeCase Dismissed
Verdict causeInfringement Action
BasisCase Dismissed
Prior Art Intelligence
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Case data sourced from PACER / Massachusetts District Court via PatSnap Eureka Litigation Intelligence Explore similar cases ↗
Case timeline

Filing to Case Dismissed in 195 days

195 days — resolved before any merits ruling, consistent with early-stage dismissal

Case timeline: Complaint filed AUG 26 2022 — 195 days total Horizontal timeline showing the three key events in Bell Semiconductor, LLC v Skyworks Solutions, Inc. from filing to resolution. Source: PACER, Massachusetts District Court. AUG 26 2022 Complaint filed Pre-trial proceedings MAR 9 2023 Case Dismissed 195 DAYS TOTAL
Patent at issue

US7149989B2 & US7260803B2 — IC dummy metal insertion and design validation

Publication No.US7149989B2
Application No.US10/947498
Patent details
ProductIncremental dummy metal insertion in integrated circuit layout design
Cited in actionAugust 26, 2022

Publication No.US7260803B2
Application No.US10/683369
Patent details
ProductEarly physical design validation and identification of metal short circuits in IC design
Cited in actionAugust 26, 2022
Technical brief · sourced from PatSnap patent database
US7149989B2Primary patent
Patent figurePatent figure
Technology summary
The method addresses the inefficiencies in late design fault detection by generating a specific rule deck for early physical design validation, focusing on texted metal short circuits and power distribution, which reduces processing time and improves the integrated circuit design flow by enabling earlier error correction.
Representative claim (1 of 2 independent)
1. A method comprising steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits between different signal sources in addition to power and ground in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific r…
Technical background
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of verifying an integrated circuit design to ensure adherence to process rules and overall manufacturability of the integrated circuit design for a specific technology. 2. Description of Related Art Physical design validation of an integrated circuit design is an important aspect of the overall…
Patent family
2 family members across 1 jurisdiction (US)
PatSnap Eureka · FTO Search Agent
Should your IC design flow be cleared against US7149989B2 and US7260803B2?

Any organisation involved in physical IC layout — particularly those using automated dummy metal fill or DRC-based short-circuit detection in their EDA flows — should consider whether their processes fall within the claims of US7149989B2 or US7260803B2. The patents cover methodologies that are broadly embedded in modern physical design toolchains, meaning exposure is not limited to chip manufacturers alone: EDA vendors and design services firms may also be at risk.

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Official verdict

Official order — verbatim text

The Case is ordered dismissedwithout prejudice with leave forthe plaintiff to file within 30 days a motion forleave to file an amended complaint. The defendant shallrespondwithin 14 days. The case is ordered administratively closed andmay be reopened uponmotion upon conclusion of ITCInvestigation.
Source: PACER Docket, Case 1:22-cv-11390, Massachusetts District Court

The court's order dismissed the action without prejudice and administratively closed the case pending an ITC Investigation, granting Bell Semiconductor 30 days to move for leave to file an amended complaint and requiring Skyworks to respond within 14 days. This procedural posture — dismissal without prejudice coupled with administrative closure — means no infringement finding was made and the substantive claims remain unresolved.

PACER case 1:22-cv-11390 · Public docket record Explore in Eureka ↗
Dismissal terms

Dismissed without prejudice: what the court's order means for both parties

Legal mechanism

Without prejudice dismissal preserves Bell Semiconductor's right to refile

A dismissal without prejudice does not adjudicate the merits of the infringement claims. The court's order expressly granted Bell Semiconductor leave to seek amendment within 30 days, meaning the litigation door remains open. Administrative closure pending the ITC Investigation means the district court action can be reopened by motion once the ITC proceedings conclude.

No merits determination
Patent holder outcome

Bell Semiconductor retains the right to pursue its IC design claims

The without-prejudice dismissal means Bell Semiconductor's patents — US7149989B2 and US7260803B2 — remain enforceable and unchallenged on the merits by this order. The leave-to-amend provision suggests the court identified pleading deficiencies rather than substantive patent invalidity. Bell Semiconductor may refile or amend if the ITC proceedings support its litigation posture.

Patents remain in force
Defendant outcome

Skyworks escapes immediate liability but faces lingering ITC and re-filing risk

Skyworks Solutions benefits from the dismissal in the short term — no injunction, no damages award, and no infringement finding. However, the administrative closure tied to the ITC Investigation means the district court action could be reinstated. Skyworks remains exposed to whatever outcome emerges from the parallel ITC proceedings, which typically focus on import exclusion relief.

ITC proceedings ongoing
Commercial implications

Parallel ITC–district court strategy is common in semiconductor IP enforcement

This case is consistent with a coordinated enforcement pattern where patent holders file parallel ITC and district court actions. The ITC route offers faster proceedings and the prospect of exclusion orders, which can be commercially decisive in semiconductor supply chains. Companies in the IC design and EDA tooling space should monitor ITC Investigation outcomes involving Bell Semiconductor's portfolio.

Parallel ITC strategy
Legal analysis based on PACER docket records for case 1:22-cv-11390 and PatSnap Eureka litigation intelligence Search PatSnap Eureka ↗
Parties and representation

Full party and counsel information

RoleNameTypeDetail
PlaintiffBell Semiconductor, LLCCompanyPatent licensing entity — holder of US7149989B2 and US7260803B2 in IC designSearch in Eureka ↗
DefendantSkyworks Solutions, Inc.CompanySkyworks Solutions, Inc. — semiconductor manufacturer specialising in analog and mixed-signal ICsSearch in Eureka ↗
Plaintiff counselAlexandra Figari EasleyAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselAshley N. MooreAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselDavid SochiaAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselRaymond P. AusrotasAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselRichard A. KamprathAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselWilliam F. McGonigle , IIIAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmArrowood LLPLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmMcKool Smith PCLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmMichelman & Robinson, LLPLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Defendant counselJames M. DowdAttorneyCounsel for Skyworks Solutions, Inc.Search in Eureka ↗
Defendant counselStephanie LinAttorneyCounsel for Skyworks Solutions, Inc.Search in Eureka ↗
Defendant law firmWilmer Hale LLPLaw FirmRepresenting Skyworks Solutions, Inc.Search in Eureka ↗
Defendant law firmWilmerHale LLPLaw FirmRepresenting Skyworks Solutions, Inc.Search in Eureka ↗
Presiding judgeJudge Allison D. BurroughsJudgeMassachusetts District CourtSearch in Eureka ↗
R&D signals

R&D signals in the IC physical design and dummy metal IP space

Forward-looking patent and R&D intelligence derived from Bell Semiconductor's assertions against Skyworks Solutions in IC dummy metal and design validation technology.

Patent portfolio

Bell Semiconductor's IC design patent portfolio signals broad enforcement scope

Bell Semiconductor holds patents derived from legacy Bell Labs and Lucent Technologies R&D in semiconductor process and design. Beyond US7149989B2 and US7260803B2, the portfolio likely contains additional claims covering physical design, metal density management, and DRC methodologies. Mapping the full portfolio scope is essential for any company in the IC physical design supply chain.

Portfolio landscape
Technology landscape

Dummy metal fill and IC density management: active filing zone

Patent filings around automated dummy metal insertion and CMP (chemical mechanical planarisation) fill optimisation have increased as advanced process nodes demand tighter metal density compliance. EDA tool vendors and foundry process teams are active filers in this space. Monitoring new publications in CPC class H01L 21/3205 and G06F 30/398 can surface competitor R&D directions.

Active filing zone
Competitor IP posture

Skyworks Solutions' own physical design IP position in analog/RF ICs

Skyworks Solutions is an active filer in analog, RF, and mixed-signal semiconductor design. Understanding Skyworks' own patent filings in physical layout, dummy structure placement, and design rule compliance may reveal design-around strategies or defensive publication activity that emerged in response to Bell Semiconductor's enforcement actions.

Defensive IP activity
White space opportunity

AI-driven DRC and physical verification: emerging patent white space

Machine learning approaches to design rule checking, metal short-circuit prediction, and automated fill optimisation represent a rapidly evolving area adjacent to the asserted patents. While US7149989B2 and US7260803B2 cover deterministic algorithmic methods, AI/ML-based physical verification approaches may represent patentable white space for EDA innovators and IC design automation teams.

AI/ML white space
Related litigation

Similar IC design patent infringement cases in US district courts

Explore comparable patent infringement actions involving integrated circuit physical design and EDA methodologies filed in US district courts and before the ITC.

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Bell Semiconductor, LLC patent enforcement history, Massachusetts District Court case history, Bell Semiconductor, LLC's full IP portfolio, and comparable case analysis
Bell Semiconductor v. othersIC dummy fill patent casesITC semiconductor exclusionsEDA method patent suits
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Strategic implications

What this case signals for the semiconductor IC design IP landscape

Bell Semiconductor's parallel enforcement strategy across the ITC and district courts signals active monetisation of legacy IC design IP.

Legacy IC design patents are being actively weaponised against chip makers

Bell Semiconductor's assertion of dummy metal insertion and IC validation patents against a major analog semiconductor company signals that legacy process-level IP remains commercially viable. Semiconductor firms should audit exposure to foundational IC physical design patents, particularly those covering EDA-adjacent methodologies.

ITC parallel filings can force administrative closure of district court actions

The court's administrative closure pending ITC proceedings reflects a well-established enforcement tactic. For semiconductor defendants, an ITC Investigation running in parallel to district court litigation can extend uncertainty and increase litigation costs significantly, even when the district court action is nominally closed.

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Frequently asked questions

Bell v Skyworks — key questions answered

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Stay ahead of IC design patent enforcement — run your FTO now

Bell Semiconductor's parallel ITC and district court strategy signals ongoing enforcement risk for IC designers and EDA users. Use PatSnap Eureka to map your exposure to US7149989B2, US7260803B2, and related portfolio patents before proceedings reopen.

Disclaimer

This page is compiled from public court dockets and third-party patent and litigation data via PatSnap Eureka, and is provided for general informational purposes only. The information shown — including party names, patent and application numbers, dates, case status, outcomes, and any analysis — may be incomplete, may not reflect the most recent filings or legal status, and may contain errors or omissions. Verify all details against official court records (for example, PACER) and the relevant patent office before relying on them.

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