Book a demo

Cut patent&paper research from weeks to hours with PatSnap Eureka AI!

Try now
Bell Semiconductor v. Socionext America — Patent Transfer | PatSnap
Patent Litigation

Bell Semiconductor v. Socionext America: Case Transferred to N.D. California

Bell Semiconductor filed a patent infringement action against Socionext America in the Eastern District of Michigan asserting two semiconductor process patents. After 422 days, the court granted Socionext's motion to transfer all three related cases to the Northern District of California, finding that most transfer factors favored the move.

Resolution time
422days
422 days in E.D. Michigan before transfer order — litigation now continues in N.D. California
Patents asserted
2
US7007259B2 and US6436807B1 — semiconductor interconnect layer and clock-net dummy metal methods
Outcome
Case Transferred
All three related cases transferred to U.S. District Court for the Northern District of California
Cost ruling
Pending
Remaining motions were still pending at time of transfer; no cost ruling recorded in E.D. Michigan
Published by PatSnap Insights Team · Verified by PatSnap Eureka Data
Case overview

Semiconductor process patent suit shifts venue to Silicon Valley

Bell Semiconductor, LLC filed suit against Socionext America, Inc. in the Eastern District of Michigan on April 27, 2022, asserting infringement of US7007259B2, which covers a method for making an interconnect layer in a semiconductor device, and US6436807B1, which covers a method for providing clock-net aware dummy metal using dummy regions. The complaint was one of at least three related actions filed by Bell Semiconductor in the same court around the same period (case nos. 22-cv-10906, 22-cv-12018, and 22-cv-12749).

The recorded Basis of Termination for this case is 'Case Transferred.' The court's order states that Defendant's Motion to Transfer was GRANTED after the court concluded that most factors either favored transfer or were neutral, and directed the Clerk to transfer all three related cases to the U.S. District Court for the Northern District of California. No merits ruling was issued in the Eastern District of Michigan; the remaining motions were explicitly left pending at the time of transfer.

The transfer order was entered on June 23, 2023, approximately 422 days after filing — a timeline consistent with typical venue motion practice in patent cases. The Northern District of California is a preferred venue for semiconductor IP disputes given its proximity to Silicon Valley's technology ecosystem. The specific terms of any ongoing proceedings, scheduling, or substantive rulings in N.D. California are not available in the present record.

See Complete Case & Patent Analysis →
Case at a glance
CourtMichigan Eastern District Court
JudgeN/A
FiledApril 27, 2022
ClosedJune 23, 2023
Duration422 days
OutcomeCase Transferred
Verdict causeInfringement Action
BasisCase Transferred
Prior Art Intelligence
See what prior art exists on this patent.
Eureka scans millions of patents and papers to surface prior art that may have invalidated these claims before costly litigation begins.
Check Prior Art
Case data sourced from PACER / Michigan Eastern District Court via PatSnap Eureka Litigation Intelligence Explore similar cases ↗
Case timeline

Filing to Case Transferred in 422 days

422 days in E.D. Michigan before transfer order — litigation now continues in N.D. California

Case timeline: Complaint filed APR 27 2022 — 422 days total Horizontal timeline showing the three key events in Bell Semiconductor, LLC v Socionext America, Inc. from filing to resolution. Source: PACER, Michigan Eastern District Court. APR 27 2022 Complaint filed Pre-trial proceedings JUN 23 2023 Case Transferred 422 DAYS TOTAL
Patent at issue

US7007259B2 & US6436807B1 — semiconductor fabrication process patents

Publication No.US7007259B2
Application No.US10/632622
Patent details
ProductMethod for making an interconnect layer in a semiconductor device
Cited in actionApril 27, 2022

Publication No.US6436807B1
Application No.US09/484310
Patent details
ProductMethod for providing clock-net aware dummy metal using dummy regions
Cited in actionApril 27, 2022
Technical brief · sourced from PatSnap patent database
US7007259B2Primary patent
Patent figurePatent figure
Technology summary
The software tool for dummy metal insertion prioritizes regions not adjacent to clock nets, ensuring maximum distance and meeting density requirements in a single run, addressing the inefficiencies of traditional methods by minimizing timing impact on clock nets.
Representative claim (1 of 3 independent)
1. A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the method comprising: (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.
Technical background
FIELD OF THE INVENTION The present invention relates to methods for patterning dummy metal to achieve planarity for chemical-mechanical polishing of integrated circuits, and more particularly to a dummy fill software tool that provides clock-net aware dummy metal using dummy regions. BACKGROUND OF THE INVENTION Chemical Mechanical Polishing (CMP) is a part of the chip fabrication process that requires a uniform distribution of metal and silicon over the surface of the chip. To achieve this distribution, pieces of i…
Patent family
2 family members across 1 jurisdiction (US)
PatSnap Eureka · FTO Search Agent
Should you run an FTO analysis against US7007259B2 and US6436807B1?

Semiconductor design teams, EDA software vendors, and foundry customers whose products or tool outputs involve interconnect layer formation or clock-net aware dummy metal fill should assess their exposure to these two Bell Semiconductor patents. Given the patents' broad process-method framing and Bell Semiconductor's active multi-defendant assertion strategy, an FTO analysis is prudent before tape-out or product launch in affected technology nodes.

Run FTO in Eureka
Patent data sourced from USPTO via PatSnap Eureka patent database Search patent records in Eureka ↗
Official verdict

Official order — verbatim text

The Court concludes that most of the factors either favor transfer or are neutral. Thus, IT IS HEREBY ORDERED that Defendant’s Motion to Transfer (22-cv-10906, ECF No. 37; 22-cv-12018, ECF No. 31; 22-cv-12749, ECF No. 25) is GRANTED. The remaining motions in these matters remain pending. The Clerk of Court is DIRECTED to TRANSFER case numbers 22-cv-10906, 22-cv-12018, and 22-cv-12749 to the U.S. District Court for the Northern District of California.
Source: PACER Docket, Case 2:22-cv-10906, Michigan Eastern District Court

The court's transfer order is a procedural disposition, not a merits ruling. The court found that most § 1404(a) convenience factors — which typically encompass witness location, evidence access, and the interest of justice — favored the Northern District of California. All three related Bell Semiconductor actions were transferred simultaneously, and all remaining substantive motions were expressly left pending, meaning infringement and validity issues remain fully unresolved.

PACER case 2:22-cv-10906 · Public docket record Explore in Eureka ↗

What a transfer means

No merits ruling — the case moves, not ends

A transfer under 28 U.S.C. § 1404(a) relocates the entire action to a more convenient forum. The Eastern District of Michigan issued no judgment on infringement, validity, or damages. Every substantive motion left pending at the time of transfer travels with the case to the Northern District of California, where proceedings continue under a new docket.

Venue change, not dismissal
Plaintiff outlook

Bell Semiconductor must re-litigate in a new forum

Bell Semiconductor retains all its infringement claims but must now pursue them in the Northern District of California. N.D. California's Patent Local Rules impose structured claim-construction and discovery schedules. The transfer resets scheduling and may affect litigation cost and strategy, though the merits of the asserted patents remain fully alive.

Claims survive transfer
Defendant outlook

Socionext secures its preferred home-court forum

Socionext America successfully argued that most convenience factors favored California. Litigating in N.D. California — proximate to semiconductor industry witnesses, evidence, and expertise — is generally more favorable for technology defendants. Substantive defenses on infringement and validity remain to be litigated in the new forum.

Venue win for defendant
Commercial implications

Three related Bell Semiconductor cases now consolidated in N.D. Cal.

The simultaneous transfer of three related Bell Semiconductor actions to N.D. California concentrates the patent risk in a single, technically sophisticated court. Companies operating in semiconductor interconnect and clock-net design should monitor the N.D. California docket, as claim-construction rulings there will determine the practical scope of both asserted patents.

Monitor N.D. Cal. docket
Legal analysis based on PACER docket records for case 2:22-cv-10906 and PatSnap Eureka litigation intelligence Search PatSnap Eureka ↗
Parties and representation

Full party and counsel information

RoleNameTypeDetail
PlaintiffBell Semiconductor, LLCCompanyPatent assertion entity — holder of US7007259B2 and US6436807B1, semiconductor process patentsSearch in Eureka ↗
DefendantSocionext America, Inc.CompanySocionext America, Inc. — U.S. subsidiary of semiconductor SoC design company Socionext Inc.Search in Eureka ↗
Plaintiff counselCasey Lynne ShomakerAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselChristopher Reed ClaytonAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselEric A. BeanAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselJason Michael WejnertAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselKristin LeveilleAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselPatrick G. SeyferthAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselRobyn T. WilliamsAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselSusan M. McKeeverAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff counselWilliam EllermanAttorneyCounsel for Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmBush Seyferth & Paige PLLCLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmDevlin Law Firm LLCLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Plaintiff law firmMcKool Smith PCLaw FirmRepresenting Bell Semiconductor, LLCSearch in Eureka ↗
Defendant counselA. Max OlsonAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselAkira IrieAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselDaniel D. QuickAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselHui ZhaoAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselJeffrey MillerAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselJohn S. ArtzAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselKrista S. SchwartzAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselMark L. WhitakerAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselMatthew FreimuthAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant counselTeresa Truong PhamAttorneyCounsel for Socionext America, Inc.Search in Eureka ↗
Defendant law firmArnold & Porter Kaye Scholer LLPLaw FirmRepresenting Socionext America, Inc.Search in Eureka ↗
Defendant law firmDickinson Wright PLLCLaw FirmRepresenting Socionext America, Inc.Search in Eureka ↗
Defendant law firmMorrison & Foerster LLPLaw FirmRepresenting Socionext America, Inc.Search in Eureka ↗
Defendant law firmWillkie Farr & Gallagher LLPLaw FirmRepresenting Socionext America, Inc.Search in Eureka ↗
Presiding judgeJudge N/AJudgeMichigan Eastern District CourtSearch in Eureka ↗
R&D signals

R&D signals in semiconductor interconnect and dummy-fill IP

Forward-looking patent intelligence on Bell Semiconductor's portfolio, Socionext's IP posture, and innovation trends in semiconductor interconnect and clock-net dummy metal technology.

Patent portfolio

Bell Semiconductor's broader semiconductor process assertion portfolio

Bell Semiconductor holds patents spanning multiple semiconductor fabrication process domains beyond these two asserted patents. Tracking its filing activity and assignment history — particularly patents originating from legacy semiconductor IP transfers — can reveal which additional process methods may be next in its enforcement campaign against fabless SoC designers.

Assertion portfolio watch
Technology landscape

Filing trends in clock-net aware dummy metal fill technology

Clock-net aware dummy fill is an active area of EDA and physical design innovation. Patent filings from EDA vendors and foundries covering automated dummy insertion, signal-integrity-aware fill algorithms, and advanced-node planarity methods are growing. Understanding where the claim space is crowded — and where white space exists — is essential for R&D teams developing next-generation layout tools.

EDA dummy fill filing trends
Competitor IP posture

Socionext's patent portfolio in SoC interconnect design

Socionext Inc. — the parent of defendant Socionext America — is an active filer in SoC architecture and advanced interconnect design. Mapping Socionext's own patent portfolio in back-end-of-line processes and interconnect methods reveals both defensive assets relevant to this litigation and offensive IP that could be relevant in cross-licensing or future disputes in this technology space.

Socionext IP position
White space opportunity

Adjacent innovation opportunities near interconnect layer methods

The interconnect layer formation space covered by US7007259B2 involves multi-layer metallisation techniques that intersect with emerging 3D IC and chiplet integration research. Patent white space analysis around advanced packaging interconnect, through-silicon via formation, and hybrid bonding processes may reveal filing opportunities adjacent to — but outside — Bell Semiconductor's asserted claim scope.

3D IC interconnect white space
Related litigation

Similar semiconductor process patent infringement cases in N.D. California

Explore patent infringement actions involving semiconductor interconnect and dummy-fill process patents litigated in N.D. California and E.D. Michigan federal district courts.

🔍
Access 40+ similar cases in PatSnap Eureka
Bell Semiconductor, LLC patent enforcement history, Michigan Eastern District Court case history, Bell Semiconductor, LLC's full IP portfolio, and comparable case analysis
Bell Semiconductor v. othersInterconnect patent suitsDummy metal fill casesN.D. Cal. § 1404 transfers
Unlock similar cases in Eureka →
Strategic implications

What this transfer signals for semiconductor IP strategy

A successful venue transfer to N.D. California reshapes the cost, timeline, and witness calculus for both parties in this semiconductor process dispute.

Venue selection is a first-order strategic decision in semiconductor patent suits

Socionext's successful transfer motion demonstrates that challenging venue at the outset can materially shift the litigation landscape. For semiconductor companies served with infringement complaints in remote districts, a § 1404(a) transfer motion — filed promptly and supported by witness and evidence location data — is a powerful defensive tool worth prioritising above early merits motions.

Bell Semiconductor's multi-case filing pattern warrants portfolio monitoring

Bell Semiconductor filed at least three related cases in E.D. Michigan simultaneously, suggesting a coordinated assertion campaign around its semiconductor process patent portfolio. Companies in the interconnect and clock-net design space should audit their products against US7007259B2 and US6436807B1 and track Bell Semiconductor's broader filing activity for additional assertion risk.

🔒
Full strategic analysis in PatSnap Eureka
Unlock gated insights on semiconductor process patent enforcement trends and N.D. California district court strategy for this case.
Claim scope analysisBell Semiconductor portfolio riskN.D. Cal. scheduling intel
Unlock full analysis →
Analysis powered by PatSnap Eureka Litigation Intelligence Explore in Eureka ↗
Frequently asked questions

Bell v Socionext — key questions answered

Still have questions? PatSnap Eureka can answer them instantly from patent and litigation data. Ask Eureka ↗
PatSnap Eureka

Monitor Bell Semiconductor's N.D. California campaign with Eureka

Track claim-construction rulings and docket developments across all three transferred Bell Semiconductor cases in N.D. California. Run an FTO screen against US7007259B2 and US6436807B1 before your next semiconductor product tape-out.

Ask anything about this case.
PatSnap Eureka searches patents and litigation data to answer instantly.
Powered by PatSnap Eureka
Link copied to clipboard

Related Litigation Cases

Help us improve this page

Found incorrect or outdated information? Let us know and we'll get it fixed.