Bell Semiconductor v. Socionext America: Six-Patent EDA Dispute Dismissed With Prejudice
Bell Semiconductor, LLC asserted six U.S. semiconductor design patents against Socionext America, alleging infringement through use of Cadence, Synopsys, and Siemens EDA tools to design chips including the SynQuacer SC2A11. The case closed in 195 days — dismissed with prejudice on both sides — after Bell Semic settled separately with all three upstream tool vendors in parallel Delaware proceedings.
Downstream EDA-user suit collapses after all three tool-vendor disputes settle
Filed on 23 June 2023 in the Northern District of California before Judge Yvonne Gonzalez Rogers, this action saw patent assertion entity Bell Semiconductor, LLC target Socionext America, Inc. — the US arm of the Fujitsu/Panasonic-origin chip designer — over alleged infringement of six patents covering incremental ECO routing and dummy-fill rearrangement in multi-layer IC design. The accused activity centred on Socionext’s use of Cadence, Synopsys, and Siemens EDA tool suites in designing products including the SynQuacer SC2A11 processor.
The case resolved on 4 January 2024 via a stipulated dismissal with prejudice, with each party bearing its own costs. The dismissal was explicitly downstream of three separate settlements Bell Semiconductor reached with the EDA tool vendors themselves — Siemens settled in May 2023, Cadence in August 2023, and Synopsys in December 2023 — all in parallel declaratory judgment proceedings in the District of Delaware. Once all three vendor disputes were resolved with prejudice, the rationale for continuing against Socionext as an end-user effectively dissolved.
A 195-day resolution is notably swift for a six-patent district court infringement action and is consistent with a coordinated litigation strategy in which the end-user defendant case was always contingent on the vendor-level disputes. The public record does not disclose any direct financial settlement between Bell Semiconductor and Socionext, leaving open whether Socionext was covered under the vendor settlement licences or negotiated separate consideration. The with-prejudice dismissal forecloses any refiling of these specific claims by Bell Semic against Socionext on the asserted patents.
Filing to dismissal in 195 days
Days from filing to dismissal — resolved well inside the median district court patent lifecycle
Dismissed with prejudice — what the stipulated order means for both parties
Stipulated dismissal with prejudice: the case is permanently closed
A dismissal with prejudice under FRCP 41 operates as a final adjudication on the merits. Bell Semiconductor is barred from bringing the same infringement claims — on the same six patents, against Socionext America — in any U.S. federal court. The stipulated form means both parties agreed to the terms, which typically signals that Socionext was satisfied with the outcome or obtained some form of release, even if the terms are not public.
Permanent bar on refilingThree upstream vendor settlements drove the end-user dismissal
Bell Semic’s infringement theory rested on Socionext’s use of Cadence, Synopsys, and Siemens tools. Once Bell Semic settled with all three vendors — with prejudice, in Delaware — continuing the California end-user action became legally and commercially redundant. This ‘vendor-first’ enforcement pattern is common in EDA-adjacent PAE litigation: resolving tool-maker liability often extinguishes or undermines downstream user exposure, particularly where the vendor settlement includes customer coverage clauses.
Vendor-first PAE enforcement patternEach party bears its own costs — no fee-shifting
The stipulation mirrors the cost terms in all three Delaware vendor settlements (each also on own-costs terms). No party sought or obtained attorneys’ fees under 35 U.S.C. § 285 (exceptional case) or 28 U.S.C. § 1927. This is the standard commercial outcome in PAE settlement-driven dismissals, where both sides prefer a clean exit over protracted fee litigation. It does not signal any judicial finding about case merit.
No fee-shifting; clean exitDelaware DJ actions shaped the California outcome throughout
Three separate declaratory judgment actions in the District of Delaware — filed by Siemens (No. 22-1569), Cadence, and Synopsys (No. 22-1512) — ran concurrently with or preceded this California filing. The sequencing matters: the Siemens DJ settled before this California case was even filed; Cadence settled while it was pending; Synopsys settled just weeks before the California dismissal. The California action appears to have functioned as settlement leverage rather than a standalone litigation track.
Leverage litigation via parallel venuesFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Bell Semiconductor, LLC | Company | Patent assertion entity — holder of US7231626B2, US7396760B2, and four further IC-design patentsSearch in Eureka ↗ |
| Defendant | Socionext America, Inc. | Company | Socionext America, Inc. — US subsidiary of Socionext Inc., fabless SoC designer (SynQuacer line)Search in Eureka ↗ |
| Plaintiff counsel | Alex H. Chan | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Casey Lynne Shomaker | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Christopher Reed Clayton | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Jason Michael Wejnert | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Kristin Leveille | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Patrick G. Seyferth | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Susan M. McKeever | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | William Ellerman | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Defendant counsel | A. Max Olson | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Akira Irie | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Daniel D. Quick | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Hui Zhao | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Jeffrey Miller | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | John Shepherd Artz | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Krista Sue Schwartz | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Mark L. Whitaker | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Matthew Freimuth | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Roman A. Swoopes | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Defendant counsel | Teresa Truong Pham | Attorney | Counsel for Socionext America, Inc.Search in Eureka ↗ |
| Presiding judge | Judge Yvonne Gonzalez Rogers | Chief Judge | California Northern District Court — Chief JudgeSearch in Eureka ↗ |
Stipulation of dismissal — official text
The stipulated order dismisses all claims and defences of each party against the other with prejudice, mirroring the cost structure of the three Delaware vendor settlements. The with-prejudice formulation is final and merits-equivalent under FRCP 41, permanently barring Bell Semiconductor from reasserting these six patents against Socionext America. Notably, the order names all three vendor settlements by date and case number, making explicit that the California dismissal was a downstream consequence of those upstream resolutions rather than an independent merits outcome.
US7231626B2 & US7396760B2 — IC design ECO routing and dummy-fill optimisation
US7231626B2 (application no. 11/015,123) and US7396760B2 (application no. 10/991,107) are two of six Bell Semiconductor patents asserted in this action. US7231626 covers methods for incremental routing during engineering change order (ECO) flows — a critical step in late-stage IC design where designers must make targeted changes without re-running full place-and-route. US7396760 covers methods for rearranging dummy fill to minimise overlap between successive metal layers, directly addressing signal integrity and chemical-mechanical planarisation (CMP) uniformity in advanced-node designs. Both patents sit in the physical design automation domain and are directly relevant to EDA tool functionality offered by Cadence, Synopsys, and Siemens.
These patents are strategically significant because they cover foundational EDA workflow steps — not exotic edge cases — meaning virtually any advanced-node chip design project using major EDA suites could theoretically involve the claimed methods. Bell Semiconductor appears to have acquired these patents as part of a broader portfolio play targeting the EDA ecosystem from two angles simultaneously: the tool vendors (Delaware DJ) and their customers (California infringement). The continued validity of these patents post-settlement means the risk has not been extinguished for the broader semiconductor design community.
Should your design team run an FTO check against US7231626B2 and US7396760B2?
Any fabless semiconductor company, IDM, or design house using Cadence Innovus, Synopsys IC Compiler, or Siemens Calibre for ECO routing or dummy-fill operations should treat these patents as active risk. The fact that Bell Semiconductor pursued both tool vendors and an end-user simultaneously demonstrates willingness to target customers directly — even where the underlying workflow is enabled by commercially licensed software. R&D and IP teams evaluating new tape-outs or tool migrations should include Bell Semic’s portfolio in pre-production FTO scope.
PatSnap Eureka’s FTO Search Agent can map the claim scope of US7231626B2 and US7396760B2 against your specific design flows, flag related family members across jurisdictions, and monitor for new continuation filings or portfolio transfers. Given that Bell Semic’s broader six-patent portfolio includes US7007259, US7149989, US6436807, and US7260803, a full portfolio-level claim analysis — not just the two lead patents — is the appropriate scope. Set up claim change alerts to catch any prosecution activity that might broaden coverage.
Run a freedom-to-operate analysis on US7231626B2 to assess your product’s exposure
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What this case signals for the semiconductor EDA IP landscape
Bell Semiconductor’s coordinated multi-venue campaign offers a clear template — and a clear warning — for EDA tool users and vendors alike.
EDA tool users face real downstream infringement exposure from PAE campaigns
Socionext’s position — sued for using commercially licensed EDA tools — illustrates that end-users of Cadence, Synopsys, and Siemens software cannot assume vendor licences confer immunity from PAE assertions on underlying design patents. Chip designers and fabless companies should audit their EDA tool usage against active patent assertion portfolios, particularly those targeting incremental ECO routing and dummy-fill techniques.
Vendor settlements do not automatically discharge customer liability
The public record is silent on whether Socionext was expressly covered by the Cadence, Synopsys, or Siemens settlement licences. The with-prejudice dismissal may reflect that it was — or that Socionext negotiated separately. Either way, companies relying on vendor settlements for protection should seek explicit downstream customer coverage language rather than assuming it flows automatically.
Bell v Socionext — key questions answered
Bell Semiconductor asserted six U.S. patents: US7007259, US7149989, US7396760, US6436807, US7260803, and US7231626. The patents cover IC physical design methods including incremental ECO routing and dummy-fill rearrangement across successive metal layers, targeting Socionext’s use of Cadence, Synopsys, and Siemens EDA tools.
The case was dismissed with prejudice by stipulation on 4 January 2024, following Bell Semiconductor’s settlement of parallel declaratory judgment actions in the District of Delaware with all three EDA tool vendors: Siemens (May 2023), Cadence (August 2023), and Synopsys (December 2023). Once the upstream vendor disputes resolved, continuing the end-user action against Socionext became moot or commercially unnecessary.
A dismissal with prejudice under FRCP 41 is treated as a final adjudication on the merits. Bell Semiconductor is permanently barred from bringing the same infringement claims on the same six patents against Socionext America in U.S. federal court. Neither party was awarded costs, expenses, or attorneys’ fees.
The accused activities involved Socionext’s use of Cadence, Synopsys, and/or Siemens EDA tools to perform incremental routing in ECO flows and to rearrange dummy fill to minimise overlap in successive IC layers. The SynQuacer SC2A11 chip was specifically identified as an accused product designed using those tools.
Bell Semiconductor was represented by Baker Botts LLP, Bush Seyferth & Paige PLLC, Devlin Law Firm LLC, and McKool Smith PC. Socionext America was represented by Arnold & Porter Kaye Scholer LLP, Dickinson Wright PLLC, Morrison & Foerster LLP, and Willkie Farr & Gallagher LLP. The case was assigned to Judge Yvonne Gonzalez Rogers in the Northern District of California.
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