Bell Semiconductor v. Western Digital: Case Dismissed After 241 Days
Bell Semiconductor asserted two semiconductor process patents — covering interconnect layer fabrication and clock-net dummy metal techniques — against Western Digital in the Central District of California. The joint motion to dismiss was granted after just 241 days, with plaintiff's claims dismissed with prejudice and defendant's counterclaims dismissed without prejudice.
A swift joint dismissal in a two-patent semiconductor process dispute
Bell Semiconductor, LLC filed suit against Western Digital, Corp. on June 7, 2022 in the Central District of California, asserting infringement of US7007259B2 (method for making an interconnect layer and a semiconductor device including the same) and US6436807B1 (method for providing clock-net aware dummy metal using dummy regions). Both patents relate to semiconductor fabrication process techniques. Western Digital is a major manufacturer of data storage devices whose products depend on advanced semiconductor process nodes.
The recorded Basis of Termination is 'Case Dismissed.' The docket order, entered on a joint motion to dismiss (Dkt. 79), states that plaintiff's claims against defendant are dismissed with prejudice, while defendant's claims, defenses, or counterclaims against plaintiff are dismissed without prejudice. Each side bears its own attorneys' fees, costs, and expenses. A pending motion to consolidate (Dkt. 71) was simultaneously rendered moot.
Resolution within 241 days — before any trial-ready date — suggests the parties reached an understanding relatively early in the litigation lifecycle. The asymmetric dismissal structure (plaintiff with prejudice, defendant without prejudice) is notable: Bell Semiconductor cannot re-assert these specific claims against Western Digital, while Western Digital retains the ability to pursue any counterclaims it had raised. The specific commercial terms, if any, underlying the joint motion are not disclosed in the available public record.
See Complete Case & Patent Analysis →Filing to Case Dismissed in 241 days
241 days — resolved well under the typical 2–3 year district court patent trial cycle
US7007259B2 & US6436807B1 — Semiconductor Fabrication Process Patents
Any organization active in advanced semiconductor design, EDA tool development, or fabless chip production should treat these patents as live FTO considerations. US7007259B2 covers interconnect layer formation — a step present in virtually every modern IC manufacturing flow. US6436807B1 covers clock-net dummy metal insertion — a standard physical design step in timing-critical layouts. Both patents remain in force and can be asserted against parties other than Western Digital.
Official order — verbatim text
The court's order on Dkt. 79 reflects a standard good-cause finding on a joint motion, with no merits adjudication on infringement or validity. The asymmetric prejudice structure — plaintiff's claims extinguished, defendant's preserved — is the operative legal outcome. No findings on claim scope, validity, or damages were made. The specific terms underlying the parties' joint agreement are not disclosed in the available record.
Case dismissed: what the asymmetric dismissal means for both parties
Joint motion to dismiss: how this case ended
The case ended on a joint motion to dismiss filed by both parties (Dkt. 79). The court found sufficient good cause and granted it in full. A joint motion signals mutual agreement to end the litigation, though the specific terms driving that agreement are not disclosed in the public record. The court's order is the operative termination event.
Jointly agreed dismissalBell Semiconductor's claims dismissed with prejudice
Bell Semiconductor's infringement claims against Western Digital are dismissed with prejudice, meaning Bell Semiconductor cannot re-file the same claims against Western Digital in a new action. This forecloses any future infringement suit on US7007259B2 and US6436807B1 against this specific defendant. The patents themselves remain in force and may be asserted against other parties.
Claims barred against this defendantWestern Digital's counterclaims dismissed without prejudice
Western Digital's claims, defenses, or counterclaims are dismissed without prejudice, preserving the right to bring those claims in a future proceeding if circumstances arise. This asymmetry — plaintiff with prejudice, defendant without — is relatively uncommon and suggests the structure was negotiated. The specific counterclaims Western Digital had asserted are not detailed in the available public record.
Counterclaims preserved for futureAsymmetric dismissal signals a negotiated resolution framework
The split dismissal structure — plaintiff's claims extinguished, defendant's preserved — is consistent with a negotiated resolution, though specific terms are not disclosed. For the broader semiconductor process IP sector, this outcome signals that Bell Semiconductor's assertion campaign against storage device makers can be resolved short of trial. Other potential defendants in similar Bell Semiconductor actions may monitor this resolution as a data point.
Negotiated resolution signalFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Bell Semiconductor, LLC | Company | Semiconductor IP licensing entity — holder of US7007259B2 and US6436807B1Search in Eureka ↗ |
| Defendant | Western Digital, Corp. | Company | Western Digital, Corp. — global data storage and semiconductor device manufacturerSearch in Eureka ↗ |
| Plaintiff counsel | Alan P. Block | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Alex H. Chan | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Alexandra Easley | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Ashley N. Moore | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Casey L. Shomaker | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Christopher Clayton | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | David Sochia | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Richard A. Kamprath | Attorney | Counsel for Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Devlin Law Firm LLC | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | McKool Smith PC | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Michelman & Robinson LLP | Law Firm | Representing Bell Semiconductor, LLCSearch in Eureka ↗ |
| Defendant counsel | Gregory S. Cordrey | Attorney | Counsel for Western Digital, Corp.Search in Eureka ↗ |
| Defendant counsel | Joseph J. Mellema | Attorney | Counsel for Western Digital, Corp.Search in Eureka ↗ |
| Defendant counsel | Sarah Gabrielle Hartman | Attorney | Counsel for Western Digital, Corp.Search in Eureka ↗ |
| Defendant counsel | Stanley M. Gibson | Attorney | Counsel for Western Digital, Corp.Search in Eureka ↗ |
| Defendant law firm | Jeffer Mangels Butler & Mitchell, LLP | Law Firm | Representing Western Digital, Corp.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | California Central District CourtSearch in Eureka ↗ |
R&D signals in the semiconductor process IP space
Forward-looking patent and R&D intelligence derived from Bell Semiconductor's assertion of interconnect and dummy metal fabrication patents against Western Digital.
Bell Semiconductor's fabrication process patent activity
Bell Semiconductor holds patents spanning semiconductor interconnect formation, dummy fill techniques, and related physical design methodologies. Understanding the breadth and activity level of this portfolio — including any continuing applications or related family members beyond US7007259B2 and US6436807B1 — is essential for companies assessing assertion risk in advanced node design and manufacturing.
Licensing entity portfolioFiling trends in interconnect and dummy fill patent space
Patent filing activity in interconnect layer formation and CMP-aware dummy metal insertion has intensified as device geometries shrink below 10nm. Leading foundries, IDMs, and EDA vendors are actively filing in this space. Mapping the filing trajectory helps R&D teams identify crowded claim territories and anticipate future assertion vectors from both NPEs and operating companies.
Interconnect IP filing trendsWestern Digital's semiconductor process patent position
Western Digital, primarily known as a storage device manufacturer, increasingly designs and deploys advanced semiconductor components. Analyzing its own patent filings in interconnect and backend-of-line process technologies reveals how it builds defensive IP in the fabrication domain — and where its patent posture may be thin relative to assertion risk from process-IP holders.
Western Digital IP defensibilityAdjacent innovation gaps near clock-net dummy metal techniques
Clock-net aware dummy metal insertion (the subject of US6436807B1) sits at the intersection of physical design automation and process integration. Adjacent white space exists in machine-learning-assisted dummy fill optimization, multi-patterning-aware dummy strategies, and 3D-IC integration contexts — areas where filing activity remains relatively sparse and where early IP positioning could be strategically valuable.
Physical design IP white spaceSimilar semiconductor process patent assertions in C.D. California
Explore related patent infringement actions asserting semiconductor fabrication and interconnect process patents in the Central District of California.
What this case signals for the semiconductor process IP landscape
A fast-closing, asymmetric dismissal in a two-patent semiconductor fabrication dispute carries implications beyond this single docket.
Bell Semiconductor's with-prejudice dismissal bars re-assertion against Western Digital
The with-prejudice termination of Bell Semiconductor's claims means US7007259B2 and US6436807B1 cannot be re-asserted against Western Digital. Companies in Bell Semiconductor's enforcement crosshairs should assess whether early joint resolution — before claim construction — is a viable strategic option given this precedent.
241-day resolution suggests pre-trial leverage windows are short in this venue
Cases before the Central District of California frequently resolve faster than the national median when defendants engage early. The 241-day lifecycle here — from filing to joint dismissal — suggests that well-resourced defendants like Western Digital can compress the timeline significantly, limiting plaintiff discovery leverage.
Bell v Western — key questions answered
Bell Semiconductor asserted two patents: US7007259B2, covering a method for making an interconnect layer and a semiconductor device including the same, and US6436807B1, covering a method for providing clock-net aware dummy metal using dummy regions. Both relate to semiconductor fabrication and physical design process techniques.
The recorded Basis of Termination is 'Case Dismissed.' The docket order granted a joint motion to dismiss: Bell Semiconductor's claims were dismissed with prejudice, Western Digital's counterclaims were dismissed without prejudice, and each side bears its own attorneys' fees, costs, and expenses. The specific terms underlying the joint agreement are not disclosed in the available public record.
Dismissal with prejudice means Bell Semiconductor cannot re-file the same infringement claims against Western Digital on US7007259B2 and US6436807B1. The claims are permanently extinguished as against this defendant. The patents remain valid and enforceable against third parties not party to this dismissal order.
The asymmetric prejudice structure — plaintiff with prejudice, defendant without — means Western Digital retains the right to pursue its counterclaims in a future proceeding. This structure is consistent with a negotiated resolution, though the specific terms driving that arrangement are not disclosed in the available public record. No court finding explains the asymmetry on the merits.
The case lasted 241 days from filing (June 7, 2022) to closure (February 3, 2023) — well under the typical 2–3 year lifecycle for patent cases proceeding to trial. Resolution this early, before any claim construction ruling, suggests the parties reached an understanding during the early litigation phase. This timeline may be relevant to other defendants facing similar early-stage assertion campaigns from IP licensing entities.
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