BeSang v. Micron: Court Rules No Infringement in 3D Memory Patent Dispute

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📋 Case Summary

Case Name BeSang, Inc. v. Micron Technology, Inc.
Case Number 2:23-cv-00028 (E.D. Tex.)
Court U.S. District Court for the Eastern District of Texas
Duration Jan 2023 – Sep 2025 2 years 8 months
Outcome Defendant Win – No Infringement
Patents at Issue
Accused Products Micron’s Crucial & Micron SSD series (e.g., BX500, MX500, P3 Plus, P5 Plus, 1100, 2100AI/AT, 2200, 2300, 2450)

Case Overview

The Parties

⚖️ Plaintiff

A patent assertion entity holding intellectual property directed at three-dimensional semiconductor memory architecture.

🛡️ Defendant

A Fortune 500 semiconductor manufacturer and global leader in DRAM, NAND flash, and solid-state storage.

Patents at Issue

This case involved U.S. Patent No. 7,378,702 B2, directed to three-dimensional semiconductor memory architecture. The pivotal element was the claim term “stackable add-on layer,” which became the central point of contention during claim construction proceedings.

  • US7,378,702 B2 — 3D semiconductor memory architecture with a “stackable add-on layer”
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The Verdict & Legal Analysis

Outcome

The court entered final judgment for Micron, finding that the accused SSD products do not infringe any claim of the ‘702 patent. No damages were awarded to BeSang, and injunctive relief was not granted. Micron’s counterclaims were dismissed without prejudice.

Key Legal Issues

The case hinged entirely on the claim construction of the term “stackable add-on layer”. The court’s interpretation of this critical term, central to BeSang’s claimed 3D memory architecture, excluded Micron’s products from the patent’s scope, leading to a finding of no literal infringement.

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⚠️ Freedom to Operate (FTO) Analysis in 3D Memory

This case highlights critical IP risks in 3D memory design. Choose your next step:

📋 Understand Litigation Impact in 3D NAND

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  • Explore the 3D NAND patent landscape
  • See which companies are most active in 3D memory IP
  • Understand claim construction patterns for core technologies
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High Risk Area

3D memory architectures with vertical integration

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Key Term Decisive

“Stackable add-on layer” construction crucial

Design-Around Options

Emphasis on structural differentiation

✅ Key Takeaways

For Patent Attorneys & Litigators

Claim construction of a single term — “stackable add-on layer” — drove total judgment for the defendant across all accused products.

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Prosecution history is vital for supporting broad claim construction and avoiding restrictive judicial interpretations.

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For IP Professionals

Patent assertion entities targeting foundational architecture in maturing tech spaces (3D NAND) face increasing claim construction risk.

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FTO analyses in semiconductor memory should account for how courts — not just USPTO examiners — construe foundational architecture terms.

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For R&D Leaders

Proactive design-around documentation and early FTO analysis are critical for new 3D memory designs.

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Focus on structural differentiation from existing patents in layered memory architectures to mitigate litigation risk.

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⚖️ Disclaimer: This article is for informational purposes only and does not constitute legal advice. The analysis presented reflects publicly available case information and general legal principles. For specific advice regarding patent litigation, FTO analysis, or IP strategy, please consult a qualified patent attorney.