Case 21-1763: Federal Circuit appeal over US8081026B1 dismissed after 655 days
An invalidity/cancellation appeal concerning US8081026B1 — a patent covering methods for supplying output supply voltage to power-gated integrated circuits — was jointly dismissed at the Federal Circuit under Fed. R. App. P. 42(b). The case ran for 655 days before the parties moved to end it, with each side bearing its own costs.
Federal Circuit invalidity appeal over power-gated IC patent ends without merits ruling
Appeal No. 21-1763 was filed at the Court of Appeals for the Federal Circuit on 19 March 2021 and closed on 3 January 2023, spanning 655 days. The underlying dispute centred on the patentability of US8081026B1 (application no. US12/787457), a patent directed to a method for supplying an output supply voltage to a power-gated circuit and an integrated circuit — a technology relevant to low-power semiconductor design. The appellate proceeding arose from an invalidity or cancellation action.
The recorded basis of termination is 'Appeal Dismissed'. The docket order states that the parties jointly moved to dismiss the appeals pursuant to Fed. R. App. P. 42(b), with each side to bear its own costs, and that the motion was granted. Because the dismissal was procedural, the Federal Circuit issued no merits ruling on the patentability of US8081026B1. The specific terms motivating the joint motion are not disclosed in the available record.
The 655-day appellate duration before a joint dismissal is notable: the parties maintained the appeal through a significant portion of its potential lifespan before agreeing to withdraw it. What prompted the joint motion — whether resolution of the underlying dispute, a licensing arrangement, or another commercial development — is not disclosed in the available record. The patent's validity status as determined by the tribunal of first instance remains the operative record, though what that underlying determination was is not stated in the available appellate record.
See Complete Case & Patent Analysis →Filing to Appeal Dismissed in 655 days
655 days from filing to dismissal at the Federal Circuit — a substantial appellate docket period
US8081026B1 — Output supply voltage method for power-gated integrated circuits
Any company designing, manufacturing, or licensing integrated circuits that incorporate power-gating techniques — particularly those involving controlled output supply voltage delivery to gated circuit blocks — should evaluate exposure to US8081026B1. This includes teams working on application processors, microcontrollers, power management ICs, and SoC subsystems where power domains are switched on and off dynamically. The patent's involvement in a Federal Circuit invalidity proceeding confirms it has been the subject of active legal scrutiny.
Official order — verbatim text
The Federal Circuit's order granted a joint motion to dismiss under Fed. R. App. P. 42(b), with costs allocated to each party respectively. This is a procedural termination: the court made no finding on the patentability of US8081026B1, and the order carries no precedential weight on the merits of the invalidity or cancellation arguments raised in the appeal.
Appeal dismissed: what the joint Rule 42(b) motion means for both parties
Joint dismissal under Fed. R. App. P. 42(b) — no merits adjudication
Fed. R. App. P. 42(b) allows parties to dismiss an appeal by filing a signed agreement or joint motion. The court's role is ministerial: it grants the motion without examining the merits. The result is that the Federal Circuit issued no ruling on whether US8081026B1 is valid or invalid. The underlying tribunal's record — whatever it held — remains the last substantive word on patentability.
Procedural dismissal, no merits rulingAppeal withdrawn — no appellate vindication on patentability
By joining the dismissal motion, the appellant foregoes any Federal Circuit ruling that might have reversed or vacated the tribunal below. Whether this reflects a strategic commercial decision, a settlement of the underlying dispute, or another factor is not disclosed in the available record. The appellant's appellate rights in this case are extinguished by the dismissal.
Appellate rights extinguishedDismissal preserves the record below without further appellate scrutiny
For the appellee, the joint dismissal means the Federal Circuit will not disturb whatever outcome was reached at the tribunal of first instance. The cost-neutral structure — each side bearing its own costs — suggests a negotiated endpoint rather than a concession by either party. No inference about the merits of the patentability challenge can be drawn from the dismissal alone.
No appellate reversal riskPatent status of US8081026B1 rests on the underlying record alone
Competitors and licensees in the power-gated integrated circuit space should note that this dismissal creates no new precedent on validity. The enforceability of US8081026B1 depends entirely on the first-instance record and any agreements reached between the parties off-record. Companies conducting FTO analysis on power management IC technology cannot rely on this Federal Circuit proceeding as a validity determination.
No new validity precedentFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Plaintiff | Individual | Appellant in Federal Circuit invalidity/cancellation appeal concerning US8081026B1Search in Eureka ↗ |
| Defendant | Defendant | Individual | Appellee in Federal Circuit appeal no. 21-1763 over power-gated integrated circuit patentSearch in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Court of Appeals for the Federal CircuitSearch in Eureka ↗ |
R&D signals in the power-gated integrated circuit IP space
Forward-looking patent and innovation intelligence derived from Case 21-1763 and the technology domain of US8081026B1 — power supply methods for power-gated semiconductor circuits.
Who holds adjacent power-gating IP in the US8081026B1 family?
Mapping the assignee portfolio around US8081026B1 and application US12/787457 can reveal whether the patent holder has continuation or divisional filings covering related power-gating methods. Portfolio breadth in this domain often determines whether a single-patent challenge — like this appeal — resolves the full competitive risk or leaves residual exposure across a larger family.
Portfolio mappingFiling trends in power-gated circuit voltage supply methods
Power gating is an evolving field driven by the push for lower leakage in advanced process nodes. Filing activity in output voltage supply control for power-gated circuits has grown alongside FinFET and gate-all-around adoption. Tracking recent applications in this space can reveal which players are staking new IP claims and where white space exists for design-around or novel contribution.
Filing trend analysisChallenger's patent position in power management IC design
The party that initiated the invalidity or cancellation challenge against US8081026B1 likely holds its own IP in the power management domain. Identifying their filing activity in power-gating, domain controller, and voltage regulation technology can signal competitive positioning and reveal whether they sought design freedom or offensive leverage in filing the challenge.
Competitor patent activityAdjacent innovation opportunities near US8081026B1's claims
Power-gated circuit architectures increasingly intersect with dynamic voltage and frequency scaling (DVFS), near-threshold computing, and always-on sensor subsystems. Areas such as fine-grained power domain granularity, fast wake-up voltage ramp methods, and adaptive body biasing near power gates represent potential white space adjacent to the claimed methods in US8081026B1, particularly at advanced nodes below 7nm.
White space identificationSimilar Federal Circuit patentability appeals in semiconductor power management IP
Explore Federal Circuit appeals involving invalidity and cancellation actions in the semiconductor power management and integrated circuit design space, comparable to Case 21-1763.
What this case signals for the power-gated IC patent landscape
A joint appellate dismissal after 655 days in a patentability challenge signals commercial resolution — but leaves the patent's validity status publicly unresolved.
Joint Rule 42(b) dismissals at the Federal Circuit signal off-record resolution
When both parties jointly move to dismiss a patentability appeal under Rule 42(b), it typically signals that the underlying commercial or licensing dispute has been addressed outside the court record. IP teams monitoring US8081026B1 should track any subsequent licensing announcements or assignment records, as the available court record discloses nothing about the terms.
No merits ruling means US8081026B1's validity remains formally unresolved at appeal level
For companies working in low-power, power-gated integrated circuit design, this dismissal does not clear — or confirm — any validity cloud over US8081026B1. An FTO assessment against this patent must engage the first-instance record directly, not this Federal Circuit docket. Relying on the appellate dismissal as a proxy for invalidity would be an error.
Plaintiff v Defendant — key questions answered
The Federal Circuit dismissed appeal no. 21-1763 by granting a joint motion filed by both parties under Fed. R. App. P. 42(b). The court issued no ruling on the merits of the patentability challenge. Each side was directed to bear its own costs. The case ran for 655 days from filing on 19 March 2021 to closure on 3 January 2023.
No. A dismissal under Fed. R. App. P. 42(b) is procedural and carries no merits determination. The Federal Circuit made no finding on the validity or invalidity of US8081026B1. The patent's status depends on the first-instance tribunal's record, which is not described in the available appellate docket. Companies cannot use this dismissal as evidence of validity or invalidity.
Fed. R. App. P. 42(b) allows an appellant to dismiss an appeal by filing a signed dismissal agreement or a joint motion with the appellee. The Federal Circuit grants such motions without reviewing the underlying merits. In patent cases, it is used when parties resolve their dispute during the appellate phase, though the terms of any such resolution remain private unless separately disclosed.
US8081026B1 (application no. US12/787457) covers a method for supplying an output supply voltage to a power-gated circuit and an integrated circuit. Power gating is a core technique for reducing leakage current in semiconductor devices by disconnecting power from inactive circuit blocks. It is widely implemented in mobile, IoT, and data-centre chips, making patents in this space relevant to a broad range of semiconductor manufacturers and IP licensees.
Yes. Because the Federal Circuit dismissed the appeal without ruling on validity, there is no appellate finding that clears or confirms any invalidity risk. Companies designing power-gated integrated circuits — particularly those involving controlled output supply voltage delivery to switched circuit blocks — should conduct an independent FTO analysis against US8081026B1's claims and the broader patent family to assess design freedom.
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