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Daedalus Prime v. Samsung Electronics — Semiconductor ITC Settlement | PatSnap
Patent Litigation

Daedalus Prime v. Samsung Electronics: ITC Settlement After 457 Days

Daedalus Prime, LLC brought an ITC Section 337 infringement action against Samsung Electronics asserting four US patents covering advanced semiconductor fabrication — including contact resistance reduction and self-aligned gate edge processes. The case settled after 457 days, closing in December 2023 without a public merits ruling.

Resolution time
457days
457 days from filing to closure — a mid-length ITC investigation timeline
Patents asserted
4
US9831306B2 and 3 further patents asserted covering contact resistance and gate-edge fabrication
Outcome
Case Settled
Parties reached a settlement; specific terms are not disclosed in the available record
Cost ruling
Not recorded
No cost or fee ruling recorded in the available public record
Published by PatSnap Insights Team · Verified by PatSnap Eureka Data
Case overview

ITC semiconductor fabrication dispute ends in settlement

On September 13, 2022, Daedalus Prime, LLC filed ITC Investigation No. 337-TA-1336 against Samsung Electronics Co., Ltd. before the United States International Trade Commission, assigned to Administrative Law Judge Monica Bhattacharyya. Daedalus Prime asserted four US patents — US9831306B2, US11251281B2, US10319812B2, and US10700178B2 — covering semiconductor fabrication technologies including contact resistance reduction employing germanium overlayer pre-contact metallisation and self-aligned gate edge and local interconnect processes.

The case was recorded as settled, with the participant disposition also recorded as settlement. The recorded basis of termination is 'Case Settled.' The investigation closed on December 14, 2023. The specific terms of the settlement are not disclosed in the available public record.

The 457-day duration is consistent with a contested ITC investigation that ran through significant procedural stages before resolution short of a final Commission ruling. What drove the parties toward settlement rather than an adjudicated outcome on the merits is not determinable from the public record. No exclusion order or cease-and-desist order was issued, as the matter resolved before any final ITC determination.

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Case at a glance
Case no.337-TA-1336
CourtUnited States International Trade Commission
JudgeMonica Bhattacharyya
FiledSeptember 13, 2022
ClosedDecember 14, 2023
Duration457 days
OutcomeCase Settled
Verdict causeInfringement Action
BasisCase Settled
Prior Art Intelligence
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Case timeline

Filing to Case Settled in 457 days

457 days from filing to closure — a mid-length ITC investigation timeline

Case timeline: Complaint filed SEP 13 2022 — 457 days total Horizontal timeline showing the three key events in Daedalus Prime, LLC v Samsung Electronics Co., Ltd. from filing to resolution. Source: EDIS (ITC Docket), United States International Trade Commission. SEP 13 2022 Complaint filed Pre-trial proceedings DEC 14 2023 Case Settled 457 DAYS TOTAL
Patent at issue

US9831306B2 — Contact resistance reduction, germanium overlayer semiconductor fabrication

Publication No.US9831306B2
Application No.US15/024750
Patent details
ProductContact resistance reduction employing germanium overlayer pre-contact metallisation
Cited in actionSeptember 13, 2022

Publication No.US11251281B2
Application No.US16/881541
Patent details
ProductSelf-aligned gate edge and local interconnect fabrication method
Cited in actionSeptember 13, 2022

Publication No.US10319812B2
Application No.US15/789315
Patent details
ProductContact resistance reduction semiconductor fabrication process
Cited in actionSeptember 13, 2022

Publication No.US10700178B2
Application No.US16/416445
Patent details
ProductSemiconductor contact metallisation and resistance reduction process
Cited in actionSeptember 13, 2022
Technical brief · sourced from PatSnap patent database
Patent figurePatent figure
Representative claim (1 of 6 independent)
1. A semiconductor structure, comprising: a semiconductor fin disposed above a substrate and having a length in a first direction; a gate structure disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction, wherein the gate structure has an uppermost surface; and a pair of gate edge isolation structures centered with the semiconductor fin, wherein a first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation st…
Technical background
CLAIM OF PRIORITY This application is a U.S. National Phase application under 35 U.S.C. §371 of International Application No. PCT/US13/076673, filed Dec. 19, 2013, entitled “SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME” the entire contents of which are incorporated herein by reference. TECHNICAL FIELD Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, self-aligned gate edge and local interconnect structures and methods of fabricati…
Patent family
38 family members across 9 jurisdictions (JP, TW, KR, US, EP, MY, SG, WO, CN)
PatSnap Eureka · FTO Search Agent
Should you run an FTO against US9831306B2 and the Daedalus Prime portfolio?

Any company involved in advanced-node semiconductor fabrication — including logic chipmakers, memory manufacturers, foundries, and equipment or materials suppliers — should assess freedom-to-operate against these four patents. The claims covering germanium overlayer contact resistance reduction and self-aligned gate edge processes are directly relevant to sub-10nm and sub-7nm process flows. Because the ITC investigation settled without a merits ruling, there is no prior adjudication to rely on for clearance.

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Official verdict

Official order — verbatim text

Participant Disposition: Settlement
Source: EDIS (ITC Docket) Docket, Case 337-TA-1336, United States International Trade Commission

The recorded participant disposition is 'Settlement' and the basis of termination is 'Case Settled.' No Initial Determination or Final Commission Determination was issued. The investigation closed without any ruling on infringement, validity, or the domestic industry requirement under Section 337 — meaning the merits of all four asserted patents remain unadjudicated as a result of this proceeding.

EDIS (ITC Docket) case 337-TA-1336 · Public docket record Explore in Eureka ↗
Settlement terms

Case settled: what the resolution means for both parties

Legal mechanism

ITC Section 337 investigation closed by settlement

A settlement at the ITC terminates the investigation before the Administrative Law Judge issues an Initial Determination and before the Commission issues any exclusion or cease-and-desist order. No finding on infringement, validity, or domestic industry is made. The case closes without any binding ruling on the merits of the asserted patents.

No merits ruling issued
Patent holder outcome

Daedalus Prime avoids adjudication risk on all four patents

Settlement allows Daedalus Prime to resolve the dispute without exposing its four semiconductor patents to an ITC invalidity or non-infringement determination. The patents remain in force and unadjudicated on the merits, preserving their enforceability for potential future assertion. The specific terms agreed with Samsung are not disclosed in the available record.

Patents unadjudicated, remain enforceable
Defendant outcome

Samsung avoids exclusion order risk through agreed resolution

For Samsung, settlement avoids the most significant ITC remedy risk: a general exclusion order or limited exclusion order barring importation of accused products. No public finding of infringement was made. The specific commercial or licensing terms agreed are not disclosed in the available record.

No exclusion order entered
Commercial implications

Unadjudicated semiconductor patents remain live enforcement risk

Because no ITC determination on validity or infringement was issued, Daedalus Prime's four semiconductor fabrication patents carry no adverse estoppel from this proceeding. Competitors and supply-chain participants working in contact resistance reduction or self-aligned gate edge technology should note that these patents remain active and unadjudicated.

Ongoing FTO risk for sector
Legal analysis based on EDIS (ITC Docket) docket records for case 337-TA-1336 and PatSnap Eureka litigation intelligence Search PatSnap Eureka ↗
Parties and representation

Full party and counsel information

RoleNameTypeDetail
PlaintiffDaedalus Prime, LLCCompany/Search in Eureka ↗
DefendantSamsung Electronics Co., Ltd.Company/Search in Eureka ↗
Plaintiff counselMichael T. Renaud.AttorneyCounsel for Daedalus Prime, LLCSearch in Eureka ↗
Plaintiff law firmMintz, Levin, Cohn, Ferris, Glovsky & Popeo PCLaw FirmRepresenting Daedalus Prime, LLCSearch in Eureka ↗
Defendant counselChristopher O. GreenAttorneyCounsel for Samsung Electronics Co., Ltd.Search in Eureka ↗
Defendant law firmFish & Richardson, PC (Bos)Law FirmRepresenting Samsung Electronics Co., Ltd.Search in Eureka ↗
Presiding judgeJudge Monica BhattacharyyaJudgeUnited States International Trade CommissionSearch in Eureka ↗
R&D signals

R&D signals in advanced-node semiconductor fabrication IP

Forward-looking patent and innovation intelligence derived from Daedalus Prime's ITC assertion against Samsung across contact resistance and self-aligned gate-edge fabrication technology.

Patent portfolio

Daedalus Prime's semiconductor fabrication patent family

Daedalus Prime asserted four patents spanning contact resistance reduction and self-aligned gate edge processes. Monitoring the broader family — including continuations, divisionals, and related applications from the same priority chains — is essential for any company active in advanced-node logic or memory fabrication. The portfolio's technical breadth across multiple critical process steps suggests a deliberate IP assembly strategy.

Portfolio monitoring signal
Technology landscape

Filing trends in contact resistance reduction at advanced nodes

Contact resistance at source/drain contacts is a principal performance bottleneck at sub-7nm nodes. Patent filing activity around germanium overlayer metallisation, low-resistance contact schemes, and self-aligned contact processes has intensified as the industry pushes toward 3nm and below. Tracking filing trends in this space helps R&D teams identify crowded claim territory and emerging white space.

Active filing landscape
Competitor IP posture

Samsung's defensive patent position in advanced fabrication

Samsung Electronics maintains an extensive internal patent portfolio in advanced-node semiconductor processes, including contact and interconnect technologies. Analysing Samsung's own filing activity in contact resistance reduction and local interconnect fabrication reveals the competitive defensive perimeter it builds around its process R&D — and may indicate design-around directions relevant to other industry participants.

Defensive portfolio signal
White-space opportunity

Adjacent R&D space near self-aligned gate edge and local interconnect

Self-aligned gate edge formation and local interconnect patterning sit adjacent to emerging CFET and backside power delivery architectures. Patent density analysis around these process steps may reveal under-claimed white space where R&D investment could generate defensible IP — particularly as the industry transitions to gate-all-around and 2D materials integration at leading-edge nodes.

White-space R&D opportunity
Related litigation

Similar ITC Section 337 semiconductor fabrication patent cases

Explore ITC investigations involving semiconductor process patents, contact resistance technology, and advanced-node fabrication infringement actions before the United States International Trade Commission.

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Daedalus Prime, LLC patent enforcement history, United States International Trade Commission case history, Daedalus Prime, LLC's full IP portfolio, and comparable case analysis
ITC semiconductor patent casesContact resistance IP disputesSamsung ITC 337 proceedingsGate-edge fabrication patent suits
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Strategic implications

What this case signals for the semiconductor fabrication IP landscape

An ITC settlement over advanced process-node patents, with no merits ruling, leaves the competitive IP picture unresolved for the sector.

ITC remains a high-leverage venue for semiconductor process patents

Daedalus Prime's choice of the ITC — where exclusion orders are the primary remedy — signals that contact resistance and gate-edge fabrication patents can carry genuine import-blocking threat value. Companies sourcing or importing advanced-node semiconductor products should treat unadjudicated ITC patents as live risk, not resolved risk.

Settlement without merits ruling preserves future assertion optionality

All four asserted patents exit this investigation without any adverse validity or infringement finding. That outcome is commercially significant: Daedalus Prime retains full freedom to assert these patents against other parties in future proceedings, at the ITC or in district court, without any estoppel arising from this case.

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Full strategic analysis in PatSnap Eureka
Unlock full strategic analysis for this ITC semiconductor fabrication dispute, including enforcement risk mapping and portfolio signals.
Portfolio continuation riskNext likely assertion targetsFTO gaps at sub-7nm nodes
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Analysis powered by PatSnap Eureka Litigation Intelligence Explore in Eureka ↗
Frequently asked questions

Daedalus v Samsung — key questions answered

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Map your advanced-node fabrication exposure against Daedalus Prime's patents

With four semiconductor fabrication patents unadjudicated after this ITC settlement, the enforcement risk remains live. Use PatSnap Eureka to run FTO analysis and monitor the Daedalus Prime portfolio for continuation activity.

Disclaimer

This page is compiled from public court dockets and third-party patent and litigation data via PatSnap Eureka, and is provided for general informational purposes only. The information shown — including party names, patent and application numbers, dates, case status, outcomes, and any analysis — may be incomplete, may not reflect the most recent filings or legal status, and may contain errors or omissions. Verify all details against official court records (for example, PACER) and the relevant patent office before relying on them.

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