Daedalus Prime v. Samsung Electronics: ITC Settlement After 457 Days
Daedalus Prime, LLC brought an ITC Section 337 infringement action against Samsung Electronics asserting four US patents covering advanced semiconductor fabrication — including contact resistance reduction and self-aligned gate edge processes. The case settled after 457 days, closing in December 2023 without a public merits ruling.
ITC semiconductor fabrication dispute ends in settlement
On September 13, 2022, Daedalus Prime, LLC filed ITC Investigation No. 337-TA-1336 against Samsung Electronics Co., Ltd. before the United States International Trade Commission, assigned to Administrative Law Judge Monica Bhattacharyya. Daedalus Prime asserted four US patents — US9831306B2, US11251281B2, US10319812B2, and US10700178B2 — covering semiconductor fabrication technologies including contact resistance reduction employing germanium overlayer pre-contact metallisation and self-aligned gate edge and local interconnect processes.
The case was recorded as settled, with the participant disposition also recorded as settlement. The recorded basis of termination is 'Case Settled.' The investigation closed on December 14, 2023. The specific terms of the settlement are not disclosed in the available public record.
The 457-day duration is consistent with a contested ITC investigation that ran through significant procedural stages before resolution short of a final Commission ruling. What drove the parties toward settlement rather than an adjudicated outcome on the merits is not determinable from the public record. No exclusion order or cease-and-desist order was issued, as the matter resolved before any final ITC determination.
See Complete Case & Patent Analysis →Filing to Case Settled in 457 days
457 days from filing to closure — a mid-length ITC investigation timeline
US9831306B2 — Contact resistance reduction, germanium overlayer semiconductor fabrication


Any company involved in advanced-node semiconductor fabrication — including logic chipmakers, memory manufacturers, foundries, and equipment or materials suppliers — should assess freedom-to-operate against these four patents. The claims covering germanium overlayer contact resistance reduction and self-aligned gate edge processes are directly relevant to sub-10nm and sub-7nm process flows. Because the ITC investigation settled without a merits ruling, there is no prior adjudication to rely on for clearance.
Official order — verbatim text
The recorded participant disposition is 'Settlement' and the basis of termination is 'Case Settled.' No Initial Determination or Final Commission Determination was issued. The investigation closed without any ruling on infringement, validity, or the domestic industry requirement under Section 337 — meaning the merits of all four asserted patents remain unadjudicated as a result of this proceeding.
Case settled: what the resolution means for both parties
ITC Section 337 investigation closed by settlement
A settlement at the ITC terminates the investigation before the Administrative Law Judge issues an Initial Determination and before the Commission issues any exclusion or cease-and-desist order. No finding on infringement, validity, or domestic industry is made. The case closes without any binding ruling on the merits of the asserted patents.
No merits ruling issuedDaedalus Prime avoids adjudication risk on all four patents
Settlement allows Daedalus Prime to resolve the dispute without exposing its four semiconductor patents to an ITC invalidity or non-infringement determination. The patents remain in force and unadjudicated on the merits, preserving their enforceability for potential future assertion. The specific terms agreed with Samsung are not disclosed in the available record.
Patents unadjudicated, remain enforceableSamsung avoids exclusion order risk through agreed resolution
For Samsung, settlement avoids the most significant ITC remedy risk: a general exclusion order or limited exclusion order barring importation of accused products. No public finding of infringement was made. The specific commercial or licensing terms agreed are not disclosed in the available record.
No exclusion order enteredUnadjudicated semiconductor patents remain live enforcement risk
Because no ITC determination on validity or infringement was issued, Daedalus Prime's four semiconductor fabrication patents carry no adverse estoppel from this proceeding. Competitors and supply-chain participants working in contact resistance reduction or self-aligned gate edge technology should note that these patents remain active and unadjudicated.
Ongoing FTO risk for sectorFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Daedalus Prime, LLC | Company | /Search in Eureka ↗ |
| Defendant | Samsung Electronics Co., Ltd. | Company | /Search in Eureka ↗ |
| Plaintiff counsel | Michael T. Renaud. | Attorney | Counsel for Daedalus Prime, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Mintz, Levin, Cohn, Ferris, Glovsky & Popeo PC | Law Firm | Representing Daedalus Prime, LLCSearch in Eureka ↗ |
| Defendant counsel | Christopher O. Green | Attorney | Counsel for Samsung Electronics Co., Ltd.Search in Eureka ↗ |
| Defendant law firm | Fish & Richardson, PC (Bos) | Law Firm | Representing Samsung Electronics Co., Ltd.Search in Eureka ↗ |
| Presiding judge | Judge Monica Bhattacharyya | Judge | United States International Trade CommissionSearch in Eureka ↗ |
R&D signals in advanced-node semiconductor fabrication IP
Forward-looking patent and innovation intelligence derived from Daedalus Prime's ITC assertion against Samsung across contact resistance and self-aligned gate-edge fabrication technology.
Daedalus Prime's semiconductor fabrication patent family
Daedalus Prime asserted four patents spanning contact resistance reduction and self-aligned gate edge processes. Monitoring the broader family — including continuations, divisionals, and related applications from the same priority chains — is essential for any company active in advanced-node logic or memory fabrication. The portfolio's technical breadth across multiple critical process steps suggests a deliberate IP assembly strategy.
Portfolio monitoring signalFiling trends in contact resistance reduction at advanced nodes
Contact resistance at source/drain contacts is a principal performance bottleneck at sub-7nm nodes. Patent filing activity around germanium overlayer metallisation, low-resistance contact schemes, and self-aligned contact processes has intensified as the industry pushes toward 3nm and below. Tracking filing trends in this space helps R&D teams identify crowded claim territory and emerging white space.
Active filing landscapeSamsung's defensive patent position in advanced fabrication
Samsung Electronics maintains an extensive internal patent portfolio in advanced-node semiconductor processes, including contact and interconnect technologies. Analysing Samsung's own filing activity in contact resistance reduction and local interconnect fabrication reveals the competitive defensive perimeter it builds around its process R&D — and may indicate design-around directions relevant to other industry participants.
Defensive portfolio signalAdjacent R&D space near self-aligned gate edge and local interconnect
Self-aligned gate edge formation and local interconnect patterning sit adjacent to emerging CFET and backside power delivery architectures. Patent density analysis around these process steps may reveal under-claimed white space where R&D investment could generate defensible IP — particularly as the industry transitions to gate-all-around and 2D materials integration at leading-edge nodes.
White-space R&D opportunitySimilar ITC Section 337 semiconductor fabrication patent cases
Explore ITC investigations involving semiconductor process patents, contact resistance technology, and advanced-node fabrication infringement actions before the United States International Trade Commission.
Related patent case — similar technology
Comparable case in the same technology domain. Patent holder and defendant reached resolution after proceedings.
SettledRelated infringement action — same court
Comparable Contact resistance reduction employing germanium overlayer pre-contact metalization-adjacent infringement action. Patent enforcement dynamics analysed in depth.
Active · District CourtRelated invalidity challenge — appellate outcome
Combined invalidity and infringement action in the same technology space. Decided after substantive proceedings.
DecidedDaedalus Prime, LLC's broader IP enforcement history
Daedalus Prime, LLC's full litigation history covering prior enforcement, licensing activity, and inter partes review proceedings.
Portfolio viewWhat this case signals for the semiconductor fabrication IP landscape
An ITC settlement over advanced process-node patents, with no merits ruling, leaves the competitive IP picture unresolved for the sector.
ITC remains a high-leverage venue for semiconductor process patents
Daedalus Prime's choice of the ITC — where exclusion orders are the primary remedy — signals that contact resistance and gate-edge fabrication patents can carry genuine import-blocking threat value. Companies sourcing or importing advanced-node semiconductor products should treat unadjudicated ITC patents as live risk, not resolved risk.
Settlement without merits ruling preserves future assertion optionality
All four asserted patents exit this investigation without any adverse validity or infringement finding. That outcome is commercially significant: Daedalus Prime retains full freedom to assert these patents against other parties in future proceedings, at the ITC or in district court, without any estoppel arising from this case.
Contact resistance and gate-edge IP: where the next assertion risk lies
The four patents span germanium overlayer contact processes and self-aligned local interconnect — technologies central to sub-7nm node fabrication. R&D teams developing advanced logic or memory at these process nodes should map their manufacturing flows against the claims of US9831306B2, US11251281B2, US10319812B2, and US10700178B2 before scaling production.
Daedalus Prime's portfolio posture warrants ongoing monitoring
As a patent licensing entity that selected four technically specific semiconductor fabrication patents for ITC assertion against Samsung, Daedalus Prime's broader portfolio and any continuation or divisional filing activity in this technology domain represents a forward-looking risk signal for the advanced-node semiconductor industry.
Daedalus v Samsung — key questions answered
Daedalus Prime asserted four US patents: US9831306B2, US11251281B2, US10319812B2, and US10700178B2. These patents cover semiconductor fabrication technologies including contact resistance reduction employing germanium overlayer pre-contact metallisation and self-aligned gate edge and local interconnect fabrication processes.
The investigation ended by settlement. The recorded basis of termination is 'Case Settled' and the participant disposition is recorded as 'Settlement.' The investigation closed on December 14, 2023, after 457 days. No Initial Determination or Final Commission Determination on infringement or validity was issued. The specific terms of the settlement are not disclosed in the available public record.
No. Because the investigation settled before any final Commission determination, no exclusion order or cease-and-desist order was entered against Samsung. The case closed without any ITC remedy being imposed.
Settlement at the ITC terminates the investigation without any merits ruling on infringement, validity, or the domestic industry requirement. No binding precedent is set. For the patent holder, the asserted patents exit the proceeding unadjudicated and fully enforceable. For the respondent, no exclusion order is entered. The settlement terms, including any licensing arrangement, are not part of the public record in this case.
Yes. Because the ITC investigation settled without any determination on validity or infringement, no adverse finding affects the enforceability of US9831306B2, US11251281B2, US10319812B2, or US10700178B2. The patents remain in force and Daedalus Prime retains the ability to assert them in future proceedings, subject to normal patent validity and enforceability defences available to any future respondent or defendant.
Map your advanced-node fabrication exposure against Daedalus Prime's patents
With four semiconductor fabrication patents unadjudicated after this ITC settlement, the enforcement risk remains live. Use PatSnap Eureka to run FTO analysis and monitor the Daedalus Prime portfolio for continuation activity.
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