Federal Circuit Affirms Invalidity in Micron v. Netlist Memory Patent Dispute
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📋 Case Summary
| Case Name | Micron Technology, Inc. v. Netlist, Inc. |
| Case Number | 24-1313 (Fed. Cir.) |
| Court | Federal Circuit, Appeal from D.C. Circuit |
| Duration | Jan 2, 2024 – Feb 20, 2026 780 days |
| Outcome | Defendant Win — Patent Invalidated |
| Patents at Issue | |
| Accused Products | Memory Modules with Data Buffering Technology |
Case Overview
In a significant ruling for the semiconductor memory industry, the U.S. Court of Appeals for the Federal Circuit affirmed the cancellation of Netlist, Inc.’s patent covering memory module data buffering technology in Micron Technology, Inc. v. Netlist, Inc. (Case No. 24-1313). The appellate court’s February 20, 2026 decision closed a 780-day legal battle initiated on January 2, 2024, delivering a decisive outcome on the patentability of U.S. Patent No. 10,489,314 B2.
For patent attorneys navigating memory patent litigation, IP professionals managing semiconductor portfolios, and R&D teams developing next-generation memory architectures, this ruling carries meaningful implications. The Federal Circuit’s affirmance of an invalidity or cancellation determination reinforces growing judicial scrutiny over memory module patents—an area where assertion activity has intensified amid fierce competition between leading chipmakers and patent assertion entities alike.
This analysis breaks down the case facts, legal reasoning, and strategic takeaways from one of the more closely watched memory patent disputes in recent years.
The Parties
⚖️ Plaintiff
One of the world’s largest manufacturers of DRAM, NAND flash, and other semiconductor memory products, headquartered in Boise, Idaho.
🛡️ Defendant
Memory technology company and active patent licensor based in Irvine, California, focused on memory module space.
The Patent at Issue
This landmark case involved U.S. Patent No. 10,489,314 B2, covering a memory module with data buffering technology. This patent relates to architectural innovations in how memory modules manage, route, and buffer data signals—critical functionality in high-performance DRAM modules such as LRDIMMs (Load-Reduced Dual In-Line Memory Modules) used in enterprise servers and data centers. The patent was registered with the U.S. Patent and Trademark Office (USPTO).
- • US 10,489,314 B2 — Memory module with data buffering technology
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued a clear and unambiguous disposition: AFFIRMED. The court ordered and adjudged that the lower tribunal’s finding—relating to the invalidity or cancellation of U.S. Patent No. 10,489,314 B2—stands. No damages award is associated with this proceeding given its patentability/cancellation posture. The affirmance effectively extinguishes Netlist’s ability to assert the ‘314 patent in its current form against Micron or any other party.
Key Legal Issues
The Federal Circuit’s review was centered on a patentability challenge—specifically an invalidity or cancellation action. In the Federal Circuit’s appellate review of USPTO post-grant proceedings, invalidity determinations are reviewed under the substantial evidence standard for factual findings (such as the scope and content of prior art) and de novo for legal conclusions (such as the ultimate determination of obviousness under 35 U.S.C. § 103). This affirmance signals that the evidentiary record and legal analysis supporting cancellation were sufficiently robust to survive appellate scrutiny, reinforcing growing judicial scrutiny over memory module patents.
Freedom to Operate (FTO) Analysis for Memory Patents
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📋 Understand This Case’s Impact
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High Risk Area
Memory module data buffering designs
47 Related Patents
In semiconductor memory space
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✅ Key Takeaways
The Federal Circuit affirmed invalidity of US10489314B2 covering memory module data buffering technology.
Search related case law →Post-grant invalidity proceedings remain the preferred defense strategy against memory patent assertions, as demonstrated by this outcome.
Explore precedents →Frequently Asked Questions
The case involved U.S. Patent No. 10,489,314 B2 (Application No. 15/857,519), covering a memory module with data buffering technology.
The Court of Appeals for the Federal Circuit affirmed the invalidity/cancellation of Netlist’s patent, closing the case on February 20, 2026, after 780 days of proceedings.
The affirmance reinforces the viability of post-grant invalidity challenges against memory module patents and may reduce Netlist’s licensing leverage across its broader patent portfolio in ongoing disputes with semiconductor manufacturers.
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References
- United States Court of Appeals for the Federal Circuit — Case 24-1313
- U.S. Patent and Trademark Office — Patent Center (US10489314B2)
- PACER Federal Court Records – Case No. 24-1313
- PatSnap — IP Intelligence Solutions for Semiconductor Companies
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.