Federal Circuit Affirms Invalidity of Hybrid Stacked IC Die Patent in Arbor Global Strategies v. Xilinx
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📋 Case Summary
| Case Name | Arbor Global Strategies, LLC v. Xilinx, Inc. |
| Case Number | 22-1552 (Fed. Cir.) |
| Court | Federal Circuit, Appeal from D.C. Circuit |
| Duration | March 21, 2022 – July 16, 2024 848 Days |
| Outcome | Defendant Win — Patent Invalidated |
| Patents at Issue | |
| Accused Products | Xilinx’s reconfigurable processor products |
Case Overview
The Parties
⚖️ Plaintiff
Patent assertion entity (PAE) focused on IP acquisition and monetization in advanced semiconductor packaging and reconfigurable processor technology.
🛡️ Defendant
World-leading developer of field-programmable gate arrays (FPGAs) and adaptive computing solutions, now a subsidiary of AMD.
Patents at Issue
This landmark case involved U.S. Patent No. 6,781,226 B2, which claims technology directed to a reconfigurable processor module comprising hybrid stacked integrated circuit die elements. This patent describes an architecture highly relevant to modern heterogeneous computing and advanced packaging.
- • US 6,781,226 B2 — Reconfigurable processor module with hybrid stacked IC die elements
- • US 6,781,226 B2 — Reconfigurable processor module with hybrid stacked IC die elements
- • US 6,781,226 B2 — Reconfigurable processor module with hybrid stacked IC die elements
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued a per curiam affirmance on July 16, 2024, upholding the determination of unpatentability for U.S. Patent No. 6,781,226 B2. No damages were awarded, and the patent was rendered unenforceable. This outcome signals meaning risk for broadly drafted semiconductor patents facing appellate scrutiny.
Key Legal Issues
The court’s decision reinforced the Federal Circuit’s rigorous approach to patentability challenges, particularly in technically complex semiconductor cases. The underlying unpatentability finding likely stemmed from a Patent Trial and Appeal Board (PTAB) inter partes review, where claims were evaluated against prior art for anticipation or obviousness under 35 U.S.C. §§ 102 or 103. This outcome highlights the substantial deference appellate panels extend to PTAB factual determinations on prior art.
Freedom to Operate (FTO) Analysis & Strategic Takeaways
This ruling highlights critical IP risks and strategic considerations for semiconductor and advanced packaging designs.
📋 Understand Semiconductor IP Risks
Learn about the specific invalidity risks and implications from this landmark litigation.
- Identify key prior art patterns in stacked ICs.
- Analyze PTAB invalidity challenge success rates.
- Understand claim drafting best practices for chiplet designs.
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High Prior Art Risk
Broad claims in stacked IC architectures
PTAB Viability
Strong defense for complex tech
Strategic Opportunity
Reinforce claim specificity in new filings
✅ Key Takeaways
Federal Circuit per curiam affirmances signal strong deference to underlying patentability findings — reversing PTAB unpatentability determinations on appeal remains an uphill challenge.
Search related PTAB cases →Invalidity/cancellation actions against stacked semiconductor die patents face a rich prior art environment; claim drafting specificity is essential.
Explore claim construction strategies →Fish & Richardson’s IPR-led defense model is a replicable template for sophisticated semiconductor defendants.
Analyze firm success rates →Frequently Asked Questions
U.S. Patent No. 6,781,226 B2 (Application No. 10/452,113), covering a reconfigurable processor module comprising hybrid stacked integrated circuit die elements.
The case was classified as an Invalidity/Cancellation Action with a basis of termination of “Unpatentable,” affirmed by the Federal Circuit in a per curiam ruling by Judges Hughes, Linn, and Stark on July 16, 2024.
It reinforces the viability of IPR-based invalidity challenges against legacy semiconductor packaging patents and signals ongoing risk for PAE assertions in technically mature technology domains.
It reinforces the viability of IPR-based invalidity challenges against legacy semiconductor packaging patents and signals ongoing risk for PAE assertions in technically mature technology domains.
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References & Related Resources
- U.S. Patent No. 6,781,226 B2 — USPTO Patent Center
- Case No. 22-1552 — PACER Federal Court Records
- Federal Circuit Patent Decisions Database
- PatSnap — IP Intelligence Solutions for Law Firms
- PatSnap — IP Intelligence for Semiconductor Industry
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.