Federal Circuit Affirms Invalidity of Viasat Flash Memory Patent Against Western Digital
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📋 Case Summary
| Case Name | Viasat Inc. v. Western Digital Corp. |
| Case Number | 24-1483 (Fed. Cir.) |
| Court | Federal Circuit, Appeal from D.C. Circuit |
| Duration | Feb 2024 – Jan 2026 691 days |
| Outcome | Defendant Win — Patent Invalidated |
| Patent at Issue | |
| Accused Products | Western Digital Flash Memory Products |
Case Overview
The Parties
⚖️ Plaintiff / Appellant
Global communications technology company known for satellite internet and networking, with a diverse patent portfolio including signal processing and data integrity technologies.
🛡️ Defendant / Appellee
One of the world’s largest data storage manufacturers, specializing in NAND flash memory, SSDs, and HDDs, with deep expertise in error correction technologies.
The Patent at Issue
This case centered on a patent covering forward error correction (FEC) technology crucial for data reliability in modern storage devices. This technology is foundational for ensuring the integrity of data stored in flash memories.
- • US8966347B2 — Forward error correction (FEC) with parallel error detection for flash memories.
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued a clean affirmance, upholding the lower tribunal’s finding that Viasat’s patent, US8966347B2, was invalid. No damages were awarded to Viasat. This outcome definitively closes the matter at the appellate level for this patent.
Key Legal Issues
The case was classified as an Invalidity/Cancellation Action, meaning Western Digital successfully challenged the patentability of US8966347B2. Invalidity defenses in flash memory error correction cases often focus on prior art (§ 102/§ 103) or written description/enablement failures (§ 112).
The Federal Circuit’s affirmance suggests that it found sufficient legal and factual basis to uphold the invalidity determination, implying the lower tribunal’s findings were not clearly erroneous or legally flawed. This highlights the high bar for patentability in technology-dense fields like flash memory error correction where extensive prior art exists.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in flash memory design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation.
- View all related patents in flash memory error correction
- See which companies are most active in this IP space
- Understand claim construction patterns for FEC technologies
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High Risk Area
Flash memory error correction (FEC)
Extensive Prior Art
In FEC and parallel processing
Careful Design-Around Needed
To avoid similar claims
✅ Key Takeaways
Federal Circuit affirmed invalidity of US8966347B2 covering parallel FEC for flash memories—strong precedent for invalidity-first defense strategies in storage IP cases.
Search related case law →Appellate reversal of invalidity findings is difficult; patent holders must build strong prosecution records before litigation.
Explore precedents →Freedom-to-operate (FTO) analyses in the flash error correction space should account for the now-invalidated US8966347B2, but engineers should remain alert to continuation patents or related family members Viasat may assert.
Start FTO analysis for my product →Design teams should document prior art foundations for ECC implementations to strengthen future invalidity defenses if needed.
Try AI patent drafting →Frequently Asked Questions
The case involved US8966347B2 (Application No. US14/086807), covering forward error correction with parallel error detection for flash memories.
The Federal Circuit affirmed an invalidity determination under a patentability/invalidity action. Specific invalidity grounds were not publicly disclosed in available case records.
The affirmance strengthens invalidity defenses in the error correction patent space, signaling that prior art density in NAND flash and FEC technology can successfully defeat patent assertions at the Federal Circuit level.
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PatSnap IP Intelligence Team
Patent Research & Competitive Intelligence · PatSnap
This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.
The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.
References
- United States Court of Appeals for the Federal Circuit — Case 24-1483
- U.S. Patent and Trademark Office — Patent Center for US8966347B2
- Cornell Legal Information Institute — 35 U.S.C. §§ 102, 103, 112
- Public Access to Court Electronic Records (PACER)
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.
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