Federal Circuit Affirms Invalidity of Viasat Flash Memory Patent Against Western Digital

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📋 Case Summary

Case NameViasat Inc. v. Western Digital Corp.
Case Number24-1483 (Fed. Cir.)
CourtFederal Circuit, Appeal from D.C. Circuit
DurationFeb 2024 – Jan 2026 691 days
OutcomeDefendant Win — Patent Invalidated
Patent at Issue
Accused ProductsWestern Digital Flash Memory Products

Case Overview

The Parties

⚖️ Plaintiff / Appellant

Global communications technology company known for satellite internet and networking, with a diverse patent portfolio including signal processing and data integrity technologies.

🛡️ Defendant / Appellee

One of the world’s largest data storage manufacturers, specializing in NAND flash memory, SSDs, and HDDs, with deep expertise in error correction technologies.

The Patent at Issue

This case centered on a patent covering forward error correction (FEC) technology crucial for data reliability in modern storage devices. This technology is foundational for ensuring the integrity of data stored in flash memories.

  • US8966347B2 — Forward error correction (FEC) with parallel error detection for flash memories.
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The Verdict & Legal Analysis

Outcome

The Federal Circuit issued a clean affirmance, upholding the lower tribunal’s finding that Viasat’s patent, US8966347B2, was invalid. No damages were awarded to Viasat. This outcome definitively closes the matter at the appellate level for this patent.

Key Legal Issues

The case was classified as an Invalidity/Cancellation Action, meaning Western Digital successfully challenged the patentability of US8966347B2. Invalidity defenses in flash memory error correction cases often focus on prior art (§ 102/§ 103) or written description/enablement failures (§ 112).

The Federal Circuit’s affirmance suggests that it found sufficient legal and factual basis to uphold the invalidity determination, implying the lower tribunal’s findings were not clearly erroneous or legally flawed. This highlights the high bar for patentability in technology-dense fields like flash memory error correction where extensive prior art exists.

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Freedom to Operate (FTO) Analysis

This case highlights critical IP risks in flash memory design. Choose your next step:

📋 Understand This Case’s Impact

Learn about the specific risks and implications from this litigation.

  • View all related patents in flash memory error correction
  • See which companies are most active in this IP space
  • Understand claim construction patterns for FEC technologies
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High Risk Area

Flash memory error correction (FEC)

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Extensive Prior Art

In FEC and parallel processing

Careful Design-Around Needed

To avoid similar claims

✅ Key Takeaways

For Patent Attorneys & Litigators

Federal Circuit affirmed invalidity of US8966347B2 covering parallel FEC for flash memories—strong precedent for invalidity-first defense strategies in storage IP cases.

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Appellate reversal of invalidity findings is difficult; patent holders must build strong prosecution records before litigation.

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PatSnap IP Intelligence Team

Patent Research & Competitive Intelligence · PatSnap

This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.

The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.

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⚖️ Disclaimer: This article is for informational purposes only and does not constitute legal advice. The analysis presented reflects publicly available case information and general legal principles. For specific advice regarding patent litigation, FTO analysis, or IP strategy, please consult a qualified patent attorney.