Federal Circuit Affirms Patent Invalidity in Micron v. Netlist Memory Module Dispute
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📋 Case Summary
| Case Name | Micron Technology, Inc. v. Netlist, Inc. |
| Case Number | 24-1312 (Fed. Cir.) |
| Court | Federal Circuit, Appeal from PTAB |
| Duration | Jan 2024 – Feb 2026 2 years 1 month |
| Outcome | Defendant Win — Patent Invalidated |
| Patents at Issue | |
| Accused Products | Memory Modules with Data Buffering |
Case Overview
The Parties
⚖️ Plaintiff
A Boise, Idaho-based semiconductor giant and one of the world’s largest producers of DRAM, NAND flash, and other memory technologies.
🛡️ Defendant
A memory technology company known for its patent assertion strategy targeting major memory manufacturers in the competitive DRAM and memory module markets.
The Patent at Issue
This case centered on the patentability of U.S. Patent No. 10,489,314 B2, covering methods and systems related to memory modules incorporating data buffering mechanisms—technology central to high-performance computing environments.
- • US 10,489,314 B2 — Memory module architecture with data buffering
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued a clean **affirmance** of the underlying invalidity or cancellation determination for U.S. Patent No. 10,489,314 B2. No damages or injunctive relief were at issue given the procedural posture of an invalidity action.
Key Legal Issues
The Federal Circuit’s analysis focused on **patentability grounds**, specifically upholding the lower tribunal’s invalidity finding. The appellate panel found Micron’s remaining arguments “unpersuasive,” indicating a failure to demonstrate reversible error in the underlying factual findings or legal conclusions. This includes prior art analysis, claim construction, and obviousness rulings central to the invalidity determination.
This decision reinforces the Federal Circuit’s general deference to PTAB factual findings on prior art and obviousness, a consistent pattern practitioners must account for when counseling clients on IPR appeal viability. Memory module patents with broad data buffering claims face heightened scrutiny when the prior art landscape is dense—a characteristic feature of DRAM architecture innovation.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks and opportunities in memory module design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific implications of this invalidity ruling.
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High Risk Area
Overlapping claim families in memory buffering
1 Patent Invalidated
Potentially reducing licensing leverage
FTO Opportunities
Expanded for some buffering architectures
✅ Key Takeaways
Federal Circuit affirmed invalidity of memory module buffering patent (US 10,489,314 B2) in Case No. 24-1312.
Search related case law →“Unpersuasive” appellate argument framing signals strong PTAB record below—quality of IPR petition construction matters enormously.
Explore PTAB analytics →Patentability challenges via PTAB continue to succeed at high rates in semiconductor technology areas with dense prior art.
Analyze PTAB success rates →Frequently Asked Questions
The case involved U.S. Patent No. 10,489,314 B2 (Application No. US15/857519), covering memory modules with data buffering technology.
The court affirmed an invalidity or cancellation determination on patentability grounds, finding Micron’s appellate arguments unpersuasive without identifying reversible error in the underlying proceeding.
It reduces Netlist’s assertable IP in the buffering space and reinforces PTAB’s effectiveness as a validity challenge venue for semiconductor patents, influencing litigation strategy across the memory industry.
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References
- USPTO Patent Center – US10489314B2
- United States Court of Appeals for the Federal Circuit – Case 24-1312
- U.S. Patent and Trademark Office – Patent Resources
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.