Oasis Tooling v. GlobalFoundries: Federal Circuit Affirms Ruling in Landmark Semiconductor EDA Patent Case
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📋 Case Summary
| Case Name | Oasis Tooling, Inc. v. GlobalFoundries U.S., Inc. |
| Case Number | 24-2086 (Fed. Cir.) |
| Court | Federal Circuit, Appeal from District Court |
| Duration | July 2024 – Feb 2026 590 days |
| Outcome | Ruling Affirmed |
| Patents at Issue | |
| Accused Products | GlobalFoundries’ DRC+ tool and open process technology (OPT) platforms |
Case Overview
The Parties
⚖️ Plaintiff
Patent-holding plaintiff asserting ownership of IP relating to design rule checking and EDA processing technologies.
🛡️ Defendant
Major U.S.-based semiconductor foundry offering advanced fabrication services to chip designers worldwide.
Patents at Issue
This landmark case involved two granted U.S. patents covering design rule checking (DRC) tools and related computational processing components:
- • US8266571B2 — Directed at design rule checking technologies involving parser, normalizer logic, syntax tree, and canonical forming modules.
- • US7685545B2 — Covering digester and reporter modules within EDA processing pipelines used to verify design conformance.
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued a definitive order: AFFIRMED. The appellate court upheld the lower court’s judgment in full, effectively closing the case in favor of the prevailing party below.
Key Legal Issues
The case proceeded as a formal infringement action, with Oasis Tooling asserting that GlobalFoundries’ DRC+ tool and OPT platforms incorporated patented technologies without authorization. In semiconductor EDA patent litigation, claim construction is often determinative. The Federal Circuit’s affirmance suggests the lower court’s claim construction and infringement findings withstood appellate scrutiny, reinforcing the validity of well-drafted EDA patents.
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⚠️ Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor EDA design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation.
- View all related EDA patents in this technology space
- See which companies are most active in semiconductor EDA patents
- Understand claim construction patterns for software-implemented tools
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High Risk Area
DRC tool architectures (parser, digester, etc.)
2 Related Patents
In semiconductor EDA space
Design-Around Options
May be available for claims
✅ Key Takeaways
For Patent Attorneys & Litigators
Federal Circuit affirmed the infringement ruling in Oasis Tooling v. GlobalFoundries, validating the lower court’s claim construction and liability analysis.
Search related case law →EDA patents with specific structural module claims (parser, syntax tree, canonical forming) can support sustained infringement assertions through appeal.
Explore precedents →For R&D Teams
Engineers and product architects developing DRC or related EDA tools should conduct FTO analyses against existing patents covering parser, syntax tree, and normalization logic before deployment.
Start FTO analysis for my product →Documenting design choices and differentiation from patented architectures contemporaneously strengthens future invalidity or non-infringement defenses.
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