HD Silicon Solutions v. Microchip Technology: Federal Circuit Affirms Invalidity
HD Silicon Solutions, LLC challenged the cancellation of US6774033B1 — a patent covering metal stack architecture for local interconnect layers — before the Federal Circuit against Microchip Technology, Inc. After 755 days of appellate proceedings, the court found all remaining arguments unpersuasive and issued a clean affirmance, leaving the invalidity ruling intact.
Federal Circuit closes HD Silicon’s challenge to interconnect patent validity
HD Silicon Solutions, LLC (HDSS) filed this Federal Circuit appeal on 13 January 2023, seeking to overturn a patentability ruling that had invalidated or cancelled US6774033B1 — a patent directed to metal stack structures used in local interconnect layers, a foundational element of semiconductor device fabrication. The defendant-appellee, Microchip Technology, Inc., a major microcontroller and mixed-signal chip manufacturer, successfully defended the lower tribunal’s finding.
On 6 February 2025, the Federal Circuit affirmed the decision below in full. The panel reviewed HDSS’s remaining arguments and found each one unpersuasive, issuing a terse but definitive affirmance. Under Federal Circuit appellate review, affirmance means the court identified no reversible legal error in the original patentability determination — the invalidity or cancellation of US6774033B1 therefore stands as the operative, final outcome.
The 755-day duration from filing to decision is consistent with moderately complex Federal Circuit patent appeals, though the brevity of the court’s written disposition — a short affirmance without extended opinion — suggests the panel viewed HDSS’s arguments as insufficiently novel to warrant elaborate rebuttal. What specific grounds HDSS advanced, and precisely which prior art or procedural basis drove the original cancellation, is not fully disclosed in the available public record.
Filing to Appeal Dismissed in 755 days
755 days — above the median duration for Federal Circuit patent appeals
Federal Circuit affirms: what the ruling means for both parties
Affirmance means no reversible error — the lower ruling stands
When the Federal Circuit affirms, it finds that the tribunal below committed no reversible legal error in its patentability analysis. The court does not re-try the case; it reviews for errors of law and, where applicable, factual findings under a deferential standard. Here, the panel explicitly noted that all of HDSS’s remaining arguments were ‘unpersuasive,’ signalling a substantive review rather than a purely procedural disposition.
Appellate affirmanceUS6774033B1 remains cancelled — HDSS’s enforcement position extinguished
For HD Silicon Solutions, the affirmance is terminal at this appellate level. The patent at issue — covering metal stack architecture for local interconnect layers — has been found invalid or cancelled, stripping HDSS of any remaining enforcement rights under it. Further challenge would require a petition for certiorari to the Supreme Court, a rarely granted avenue, or a separate proceeding on a distinct legal basis. The commercial value of HDSS’s position in this technology is materially diminished.
Patent cancelled — enforcement endedMicrochip Technology secures a clean freedom-to-operate win
Microchip Technology, Inc. emerges with the invalidity ruling confirmed at the highest specialist patent appellate level in the US. This affirmance substantially reduces the risk of re-litigation on US6774033B1 by HDSS or any successor in interest. For Microchip’s products that overlap the metal stack interconnect claims, this outcome is consistent with a cleared freedom-to-operate posture — though independent FTO analysis remains advisable for related patents in the same family or technology space.
Invalidity confirmed on appealSemiconductor interconnect IP: affirmance raises the bar for similar claims
Federal Circuit affirmances in patentability challenges to foundational semiconductor process patents signal that courts are willing to uphold cancellations of older fabrication IP. Companies active in local interconnect layer technology — particularly those facing assertion of similar metal stack patents — can point to this outcome as persuasive authority. The decision also reinforces that appellate panels will not disturb well-reasoned invalidity findings even under sustained challenge.
Strengthened prior art defenceFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | HD Silicon Solutions, LLC | Company | Patent assertion entity — holder of US6774033B1 covering semiconductor metal stack interconnect architectureSearch in Eureka ↗ |
| Defendant | Microchip Technology, Inc. | Company | Microchip Technology, Inc. — global microcontroller, DSP and mixed-signal semiconductor manufacturerSearch in Eureka ↗ |
| Plaintiff counsel | Justin J. Oliver | Attorney | Counsel for HD Silicon Solutions, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Sarah S. Brooks | Attorney | Counsel for HD Silicon Solutions, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Venable LLP | Law Firm | Representing HD Silicon Solutions, LLCSearch in Eureka ↗ |
| Defendant counsel | Brett M. Schuman | Attorney | Counsel for Microchip Technology, Inc.Search in Eureka ↗ |
| Defendant counsel | Rachel M. Walsh | Attorney | Counsel for Microchip Technology, Inc.Search in Eureka ↗ |
| Defendant counsel | Rohiniyurie Tashima | Attorney | Counsel for Microchip Technology, Inc.Search in Eureka ↗ |
| Defendant counsel | Sanjeet Dutta | Attorney | Counsel for Microchip Technology, Inc.Search in Eureka ↗ |
| Defendant law firm | Goodwin Procter LLP | Law Firm | Representing Microchip Technology, Inc.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Court of Appeals for the Federal CircuitSearch in Eureka ↗ |
Official order — verbatim text
The panel’s language — ‘We have considered HDSS’s remaining arguments and find them unpersuasive’ — is a standard Federal Circuit formulation signalling a merits review that yielded no basis for reversal. Under the appellate standard applicable to patentability determinations, legal conclusions are reviewed de novo while factual findings from the underlying tribunal attract deference. The clean, unqualified ‘AFFIRMED’ without remand or partial reversal confirms the lower decision survives in its entirety, closing the dispute at this level for both parties.
US6774033B1 — Metal stack for local interconnect layer
US6774033B1 (application number US10/287258) protects a metal stack structure used in the fabrication of local interconnect layers within semiconductor devices. Local interconnect layers are a critical element of CMOS and related process architectures, providing conductive pathways between transistors and overlying metal layers at sub-micron dimensions. The patent’s B1 designation indicates it issued without post-issuance amendment, suggesting the claims as granted are the claims at issue in this dispute.
Metal stack and local interconnect patents occupy a strategically sensitive zone in semiconductor IP because they touch manufacturing processes common across a broad range of chip types — from microcontrollers to mixed-signal and logic devices. For a company like Microchip Technology, whose product range spans precisely those categories, a valid assertion of US6774033B1 could have had wide-ranging implications. The confirmed cancellation removes that leverage entirely and may inform how similar process patents from the same technology generation are assessed in future inter partes proceedings.
Should you run an FTO analysis against US6774033B1?
US6774033B1 has been cancelled and that cancellation is now affirmed at the Federal Circuit — meaning the patent itself poses no direct infringement risk. However, product and process engineers working on metal stack architectures, local interconnect layer designs, or adjacent CMOS fabrication steps should still investigate related patents. The same inventive concepts may be covered by continuation, divisional, or continuation-in-part applications that remain in force and could be asserted independently.
PatSnap Eureka’s FTO Search Agent can map the full patent family surrounding US6774033B1, identify any surviving related applications by the same inventors or assignees, and flag live patents with claim language overlapping your interconnect process stack. For R&D teams developing next-generation local interconnect solutions, running this analysis before tape-out or product launch is the most cost-effective point to identify and design around any residual risk.
Run a freedom-to-operate analysis on US6774033B1 to assess your product’s exposure
Run FTO in Eureka →Similar Federal Circuit semiconductor patentability appeals
Federal Circuit appeals affirming invalidity of semiconductor fabrication process patents, including metal stack, interconnect layer, and CMOS manufacturing IP disputes.
What this case signals for the semiconductor interconnect IP landscape
The Federal Circuit’s terse affirmance in Case 23-1397 carries practical consequences for anyone navigating metal stack and local interconnect patent risk.
Affirmed invalidity narrows assertion risk for metal interconnect IP
With US6774033B1 cancelled and the Federal Circuit declining to disturb that finding, companies in the semiconductor fabrication space face reduced assertion exposure from this specific patent. However, related continuation or divisional patents in the same family may present residual risk and warrant monitoring.
Short appellate opinions signal low perceived merit — useful precedent for defendants
The Federal Circuit’s brief disposition — finding all arguments ‘unpersuasive’ without extended analysis — suggests the panel viewed the appeal as weak on its facts. Defendants in similar patentability challenges can cite this outcome to support early dispositive motions when facing comparable metal stack or local interconnect claims.
HD v Microchip — key questions answered
The Federal Circuit affirmed the lower tribunal’s invalidity or cancellation determination for US6774033B1 on 6 February 2025 in Case 23-1397. The panel found all of HDSS’s remaining arguments unpersuasive and issued an unqualified affirmance, leaving the cancellation of the metal stack interconnect patent intact.
US6774033B1 (application US10/287258) covers a metal stack architecture for local interconnect layers in semiconductor fabrication — a process-level patent relevant to CMOS and related chip manufacturing. HD Silicon Solutions asserted the patent’s validity against a cancellation action brought or supported by Microchip Technology, Inc., a major microcontroller manufacturer whose products likely overlap the claimed process.
The affirmance applies specifically to US6774033B1 and the cancellation proceeding appealed in Case 23-1397. It does not automatically invalidate related continuation, divisional, or sibling patents. Companies concerned about adjacent metal stack or local interconnect IP should conduct a full family analysis to identify any surviving related patents that could be asserted independently.
HD Silicon Solutions was represented by Venable LLP, with Justin J. Oliver and Sarah S. Brooks listed as counsel. Microchip Technology was represented by Goodwin Procter LLP, with Brett M. Schuman, Rachel M. Walsh, Rohiniyurie Tashima, and Sanjeet Dutta appearing as counsel of record.
Following a Federal Circuit affirmance, the primary remaining avenue is a petition for writ of certiorari to the US Supreme Court — a discretionary and rarely granted pathway. HDSS could also pursue separate proceedings if distinct legal grounds exist, but the affirmed cancellation of US6774033B1 effectively forecloses enforcement of that specific patent. The commercial value of the asserted IP position is materially extinguished by this outcome.
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