Huang v. TetraMem (25-1850): Federal Circuit Appeal Dismissed in 103 Days
Xiaohua Huang appealed against TetraMem, Inc. asserting patent USRE045259, covering hierarchical scalable priority encoding logic and circuits. The Federal Circuit dismissed the appeal for failure to prosecute — ending the action at the appellate level without any merits ruling after just 103 days.
Priority encoding patent appeal ends without a merits ruling
Xiaohua Huang filed appeal No. 25-1850 at the U.S. Court of Appeals for the Federal Circuit on 12 June 2025, asserting infringement of reissue patent USRE045259 — a patent covering hit-ahead hierarchical scalable priority encoding logic and circuits (application no. US13/355449) — against TetraMem, Inc., a company active in analog computing and memory technology. The appeal followed an underlying infringement action and represented Huang’s attempt to secure appellate review of that earlier decision.
The Federal Circuit dismissed the appeal on 23 September 2025 for failure to prosecute, closing the case after 103 days. A failure-to-prosecute dismissal is a procedural termination: the appellant did not advance the appeal in accordance with the court’s rules — typically by missing briefing deadlines — and the court dismissed accordingly. Critically, no merits ruling was issued: the Federal Circuit made no determination on whether USRE045259 is valid, infringed, or enforceable.
The 103-day duration is notably short, consistent with a dismissal occurring before full briefing was complete. The public record does not disclose why Huang failed to prosecute the appeal — whether due to resource constraints, a settlement reached outside the court record, or a strategic decision to abandon the appeal. Huang appeared pro se (self-represented), which may have contributed to procedural difficulties. TetraMem was represented by Herbert Smith Freehills Kramer (US) LLP.
Filing to Case Dismissed in 103 days
103 days — faster than the median Federal Circuit appeal lifecycle
Appeal dismissed for failure to prosecute: what this means for both parties
Failure to prosecute: a procedural end with no merits ruling
A Federal Circuit dismissal for failure to prosecute occurs when an appellant fails to comply with the court’s procedural requirements — most commonly missing the opening brief deadline. The court never reaches the substance of the appeal. This means USRE045259’s validity, scope, and infringement by TetraMem were never adjudicated at the appellate level. The underlying district court record stands, but no appellate precedent is created.
No merits adjudicationHuang loses appellate review without a ruling on the patent
For Huang, dismissal for failure to prosecute means the appeal is extinguished without the Federal Circuit ever assessing the merits of the infringement claim. Any rights Huang sought to vindicate through this appeal are now foreclosed at this level. Whether the dismissal is with or without prejudice to further proceedings depends on the specific order; the public record states only ‘Case Dismissed’, which does not resolve this distinction with certainty.
Appellate rights extinguishedTetraMem avoids an appellate merits decision on USRE045259
TetraMem, Inc. benefits from the dismissal: no adverse appellate ruling on infringement or patent validity was entered against it. However, because the dismissal was procedural rather than on the merits, TetraMem has not received a court finding that USRE045259 is invalid or not infringed. This leaves a residual — if narrow — risk that Huang or a successor could reassert the patent in a new action, subject to applicable procedural bars.
No merits win for defendantUSRE045259 remains unresolved — a latent risk for the sector
The dismissal creates an ambiguous outcome for companies working with hierarchical priority encoding logic or analog in-memory computing architectures. USRE045259 has neither been invalidated nor definitively held not-infringed. Firms in adjacent technology areas — particularly those commercialising hardware accelerators, neural processing units, or crossbar memory arrays that may rely on priority encoding logic — should treat this patent as an unresolved risk and consider proactive FTO analysis.
Patent status unresolvedFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Xiaohua Huang | Individual | Individual inventor and patent holder — holder of USRE045259 (priority encoding logic)Search in Eureka ↗ |
| Defendant | TETRAMEM, INC. | Company | TetraMem, Inc. — analog computing and in-memory processing technology companySearch in Eureka ↗ |
| Plaintiff counsel | Xiaohua Huang. | Attorney | Counsel for Xiaohua HuangSearch in Eureka ↗ |
| Defendant counsel | Daniel Noah Lerman | Attorney | Counsel for TETRAMEM, INC.Search in Eureka ↗ |
| Defendant law firm | Herbert Smith Freehills Kramer (US) LLP | Law Firm | Representing TETRAMEM, INC.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Court of Appeals for the Federal CircuitSearch in Eureka ↗ |
Official order — verbatim text
The order — ‘Appeal No. 2025-1850 is dismissed for failure to prosecute’ — is an administrative termination, not a substantive ruling. The Federal Circuit applied its procedural authority under Fed. Cir. R. 31 or analogous rules to dismiss for non-compliance, most likely a missed opening brief deadline. The phrasing imposes no finding on patent validity, claim scope, or infringement. Neither party receives collateral estoppel protection from this order. The dismissal closes the appellate record but leaves the underlying patent legally intact and potentially assertable.
USRE045259 — Hierarchical Scalable Priority Encoding Logic and Circuits
USRE045259 is a U.S. reissue patent corresponding to application US13/355449, covering hit-ahead hierarchical scalable priority encoding logic and circuits. Reissue patents are granted by the USPTO when an inventor seeks to correct errors in an issued patent — including, in some cases, broadening claims within two years of the original grant. The subject matter — priority encoding logic — relates to digital circuits that identify and encode the highest-priority active request in a set, a fundamental building block in processors, network switches, memory controllers, and hardware accelerators.
Priority encoding circuits are architecturally significant in analog and mixed-signal computing, where efficient arbitration between competing memory access requests underpins performance at scale. USRE045259’s ‘hierarchical scalable’ framing suggests claims directed at multi-level encoder trees capable of handling large input sets — directly relevant to the crossbar array architectures used in analog in-memory computing platforms like those developed by TetraMem. The patent’s reissue status and the assertion against a specialist analog computing company suggest it may be strategically positioned to capture next-generation hardware implementations.
Should your R&D team run an FTO against USRE045259?
Any team designing hierarchical priority encoders, request arbitration logic, or scalable priority circuits for use in processors, NPUs, memory controllers, crossbar arrays, or hardware accelerators should treat USRE045259 as a live FTO target. The Federal Circuit dismissal in Huang v. TetraMem provides no clearance: no court has held the patent invalid or its claims non-infringed. If your product roadmap includes analog in-memory computing or multi-level encoding architectures, a targeted FTO is warranted before product launch or scale-up.
PatSnap Eureka’s FTO Search Agent allows R&D and IP teams to map USRE045259’s claim language against your circuit architecture in minutes — identifying potential overlap, prior art candidates, and design-around options. Eureka’s patent analytics also surface the original grant history and reissue prosecution record, helping you understand how claim scope shifted and where design freedom exists. Run a structured FTO now to surface risks before they become litigation exposure.
Run a freedom-to-operate analysis on USRE045259E to assess your product’s exposure
Run FTO in Eureka →Similar Federal Circuit appeals: priority encoding and analog computing patents
Federal Circuit cases involving reissue patents, hardware logic circuits, and procedural dismissals for failure to prosecute — curated for IP teams in analog computing.
What this case signals for the analog computing and priority encoding IP landscape
A procedural dismissal rarely closes the door entirely. Here is what IP teams in hardware and analog computing should take away.
Pro se Federal Circuit appeals face high procedural attrition
Huang appeared to represent himself in this Federal Circuit appeal. Pro se appellants face a structurally elevated risk of procedural dismissal given the court’s strict briefing schedules and formatting rules. IP teams monitoring patent holders who lack legal representation should factor in this risk when assessing the credibility of appellate threats — but should not assume the underlying patent is invalid.
USRE045259 has no appellate merits ruling — it remains assertable
Because the Federal Circuit dismissed on procedure alone, no court has found USRE045259 invalid or held that TetraMem — or any other party — does not infringe. Companies developing or deploying hierarchical priority encoding logic in hardware should not treat this dismissal as a clearance event. An FTO analysis against this reissue patent remains commercially prudent.
Huang v TETRAMEM — key questions answered
It means Xiaohua Huang failed to comply with the Federal Circuit’s procedural requirements — most likely missing the opening brief deadline — causing the court to terminate the appeal without ruling on the merits. No finding on patent validity or infringement of USRE045259 was made.
Yes. The dismissal in case 25-1850 was procedural, not substantive. No court has invalidated USRE045259 or held its claims not infringed. The patent remains legally intact and potentially assertable against third parties, subject to any other proceedings not reflected in this case record.
USRE045259 covers hit-ahead hierarchical scalable priority encoding logic and circuits — digital circuits that identify and encode the highest-priority active signal in a hierarchical, scalable architecture. This technology is relevant to processors, memory controllers, network arbiters, and analog in-memory computing platforms.
Not definitively. Because the dismissal was for failure to prosecute — not on the merits — TetraMem did not receive a judicial finding of non-infringement or invalidity. While the dismissed appeal cannot be re-filed, the patent itself remains valid, and separate infringement actions by the patent holder or any successor are not automatically barred by this dismissal.
TetraMem, Inc. was represented by Daniel Noah Lerman of Herbert Smith Freehills Kramer (US) LLP. Xiaohua Huang, the appellant and plaintiff, appears to have been self-represented (pro se), which is consistent with the procedural dismissal for failure to prosecute.
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