Iida v. Intel Corp. — Dismissed With Prejudice After 594 Days
Professor Masahiro Iida asserted US6812737B2 — an Adaptive Logic Module patent — against Intel’s Stratix, Arria, Cyclone, and Agilex FPGA families in the Western District of Texas. The parties jointly moved to dismiss all claims with prejudice after 594 days of litigation, permanently closing both sides’ claims.
Joint dismissal ends ALM patent fight against Intel’s FPGA portfolio
On 24 June 2022, Professor Masahiro Iida filed suit against Intel Corporation in the Western District of Texas (Case No. 1:23-cv-00899) before Chief Judge Alan D. Albright. Iida asserted US6812737B2, a patent directed to Adaptive Logic Module architecture, against a broad sweep of Intel FPGA product lines including Stratix II, and the Stratix, Arria, Cyclone, and Agilex families — some of Intel’s most commercially significant programmable logic devices.
On 8 February 2024, Judge Albright granted the parties’ Joint Motion to Dismiss, terminating the case with prejudice on all sides. Iida’s infringement claims against Intel were dismissed with prejudice, and Intel’s counterclaims and defenses as to the Intel Products at issue were likewise dismissed with prejudice. Each party was ordered to bear its own attorneys’ fees, costs, and expenses — a cost-neutral resolution that suggests neither side secured a financial concession from the other in the public record.
At 594 days, the case ran for roughly 20 months before reaching joint dismissal — a timeline consistent with pre-trial settlement or resolution following early claim-construction or validity developments, though the public record does not disclose the underlying terms. The breadth of Intel products named in the complaint, spanning four major FPGA product families, suggests Iida’s theory was commercially ambitious; the with-prejudice dismissal on both sides is consistent with a confidential settlement, though that cannot be confirmed from the docket alone.
Filing to dismissal in 594 days
594 days — resolved faster than many multi-patent FPGA disputes in W.D. Texas
What the with-prejudice joint dismissal means for both parties
Joint motion: both sides agreed to end the case
A joint motion to dismiss means both plaintiff and defendant affirmatively requested termination — neither was compelled by a court ruling. This mutual agreement is a procedural signal that the parties likely reached some form of resolution outside court, though any private terms remain undisclosed. Judge Albright’s role was purely ministerial: granting what both parties requested.
Consensual terminationWith prejudice: Iida’s ALM claims against Intel are permanently closed
Dismissal with prejudice operates as a final adjudication on the merits under Fed. R. Civ. P. 41. Iida cannot refile the same US6812737B2 infringement claims against Intel’s named FPGA products in any federal court. Critically, Intel’s counterclaims — typically invalidity and non-infringement defenses — were also dismissed with prejudice as to the named Intel Products, which may carry implications for how Intel characterises the patent’s validity going forward.
No refiling permittedEach party bears its own costs — no fee-shifting order
The court ordered that all attorneys’ fees, costs of court, and expenses be borne by the party incurring them. In patent cases in the Western District of Texas, a prevailing party may seek fees under 35 U.S.C. § 285 in ‘exceptional’ cases. The absence of any fee award to either side is consistent with a negotiated exit rather than a contested ruling, and suggests neither party was found to have litigated in bad faith.
No § 285 fee awardIntel Products named: Stratix, Arria, Cyclone, and Agilex all released
The order specifically ties the dismissal of Intel’s counterclaims to ‘Intel Products’ — the Stratix II, Stratix, Arria, Cyclone, and Agilex FPGA families named in the complaint. This product-scoped language is notable: it confirms the litigation’s commercial reach and ensures these product lines are no longer subject to Iida’s US6812737B2 claims, providing Intel with clear freedom from this particular assertion across its current FPGA portfolio.
Full FPGA portfolio releasedFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Professor Masahiro Iida | Company | Individual academic inventor — holder of US6812737B2 (Adaptive Logic Module patent)Search in Eureka ↗ |
| Defendant | Intel, Corp. | Company | Intel Corp. — global semiconductor manufacturer and leading FPGA vendor (Stratix, Arria, Cyclone, Agilex)Search in Eureka ↗ |
| Plaintiff counsel | Ilan Rosenberg | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Plaintiff counsel | Jacob C. Cohn | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Plaintiff counsel | Joshua R. Slavitt | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Plaintiff counsel | Patrick J. Mulkern | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Plaintiff counsel | Richard D. Milvenan | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Plaintiff counsel | Travis C. Barton | Attorney | Counsel for Professor Masahiro IidaSearch in Eureka ↗ |
| Defendant counsel | Andrew James Delaplane | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Andrew T. Nguyen | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Brian Christopher Nash | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Faye Paul Teller | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Gregory P. Stone | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Heather E. Takahashi | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | J. Kain Day | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | J. Stephen Ravel | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Kelly Ransom | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Vincent Y. Ling | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Zachary M. Briers | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Presiding judge | Judge Alan D Albright | Chief Judge | Texas Western District Court — Chief JudgeSearch in Eureka ↗ |
Stipulation of dismissal — official text
The order grants a joint motion, meaning no contested verdict was issued — both parties affirmatively sought this outcome. The phrase ‘dismissed with prejudice’ applied symmetrically to Iida’s claims and Intel’s counterclaims is legally significant: it forecloses re-litigation of these specific claims on the merits. The product-scoped language tying Intel’s counterclaim dismissal to ‘Intel Products’ suggests the parties carefully defined the release perimeter, potentially preserving rights in adjacent contexts not named in the original complaint.
US6812737B2 — Adaptive Logic Module architecture for FPGA devices
US6812737B2, filed under application number US10/183590, covers an Adaptive Logic Module architecture — a fundamental building block used in field-programmable gate array (FPGA) design. ALM technology enables flexible, reconfigurable logic cells that can be programmed post-fabrication to implement a wide range of digital functions. The patent is attributed to Professor Masahiro Iida, an academic inventor, and its application to Intel’s major FPGA families — Stratix II, Stratix, Arria, Cyclone, and Agilex — indicates a claim scope asserted across multiple product generations and market segments.
ALM architecture is strategically central to Intel’s programmable logic business, which it inherited through the 2015 acquisition of Altera. The Stratix, Arria, Cyclone, and Agilex families collectively address data centre, automotive, aerospace, and communications markets. A foundational architecture patent asserted across these lines represents significant commercial exposure. The fact that Intel engaged a defence team from Morrison & Foerster and Munger, Tolles & Olson — both elite IP litigation firms — is consistent with treating this as a high-stakes assertion, not a routine nuisance action.
Should you run an FTO analysis against US6812737B2?
Any company designing, integrating, or licensing FPGA technology that employs Adaptive Logic Module architecture should consider a targeted freedom-to-operate review against US6812737B2. The dismissal with prejudice in this case releases only Intel and its named products — it provides no protection to other FPGA vendors, semiconductor IP licensors, or OEMs incorporating ALM-based devices in their system designs. If your product roadmap includes programmable logic built on ALM-style cell architectures, this patent warrants direct assessment.
PatSnap Eureka’s FTO Search Agent can map the claim scope of US6812737B2 against your specific product architecture, identify prior art that may bear on validity, and flag any continuation or related family members that could extend the assertion risk. Ongoing claim monitoring through Eureka will alert your team if the patent is asserted, assigned, or licensed — giving you early warning before litigation reaches your doorstep.
Run a freedom-to-operate analysis on US6812737B2 to assess your product’s exposure
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What this case signals for the FPGA and programmable logic IP landscape
An individual inventor asserting foundational logic architecture patents against a top-tier semiconductor vendor is a pattern worth tracking.
Individual inventors can credibly threaten broad FPGA portfolios in W.D. Texas
This case illustrates that a single academic inventor, armed with a foundational ALM architecture patent, can compel a company of Intel’s scale to engage seriously — and to negotiate a joint exit. W.D. Texas under Judge Albright remains an active venue for such assertions. FPGA and programmable logic teams should treat foundational architecture patents held by individual inventors as genuine litigation risk.
Joint with-prejudice dismissal may signal a licensing resolution
When both sides jointly dismiss with prejudice and each bears its own costs, the pattern is frequently consistent with a confidential licence or settlement payment — though this cannot be confirmed. Companies facing similar assertions should note that Intel did not obtain a public invalidity ruling, leaving US6812737B2 technically in force for enforcement against other defendants not covered by this order.
Professor v Intel — key questions answered
The case was dismissed with prejudice on 8 February 2024 pursuant to a joint motion by both parties. Iida’s infringement claims against Intel and Intel’s counterclaims and defenses as to the named Intel Products were all dismissed with prejudice. Each party bears its own costs.
Professor Iida accused Intel’s Adaptive Logic Module (ALM)-based FPGA products, specifically Stratix II, and the broader Stratix, Arria, Cyclone, and Agilex product families. These span Intel’s data centre, communications, and embedded FPGA segments.
The with-prejudice dismissal binds only Iida and Intel with respect to the named Intel Products. US6812737B2 remains an in-force issued US patent. Other companies using ALM-style FPGA architectures are not protected by this order and could face separate assertions.
The Western District of Texas, under Chief Judge Alan D. Albright, has been a frequently selected venue for patent infringement suits, including by individual inventors and NPEs, due to its historically plaintiff-friendly scheduling practices and significant patent docket. Intel has defended numerous patent cases in this court.
US6812737B2 covers Adaptive Logic Module (ALM) architecture used in FPGA devices — reconfigurable logic building blocks that allow post-fabrication programming. The patent is attributed to Professor Masahiro Iida, an academic inventor. The application number is US10/183590.
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