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Infineon v. Arigna: Federal Circuit Appeal Dismissed | PatSnap
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Case ID23-1708
FiledApr 2023
ClosedOct 2024
Patent Litigation

Infineon v. Arigna (23-1708): Federal Circuit Appeal Dismissed After 571 Days

Infineon Technologies AG and Arigna Technology Ltd. jointly agreed to dismiss their Federal Circuit appeal — Case No. 23-1708 — concerning the patentability of US8247867B2, a semiconductor device patent. The appeal, filed in April 2023, ended in October 2024 with each side bearing its own costs under Fed. R. App. P. 42(b).

Resolution time
571days
571 days from filing to dismissal — longer than the median Federal Circuit appeal resolution
Patents asserted
1
US8247867B2 — semiconductor device, integrated circuit architecture patent
Outcome
Voluntary dismissal
Voluntarily dismissed by agreement under FRAP 42(b); no merits ruling issued
Cost ruling
Each Side Pays
No cost award — each party bears its own litigation costs per the dismissal order
Published by PatSnap Insights Team · Verified by PatSnap Eureka Data
Case overview

A contested semiconductor patent appeal ends by mutual agreement

Infineon Technologies AG, the German semiconductor major, appealed a patentability decision involving US8247867B2 — a patent covering semiconductor device architecture — against Arigna Technology Ltd. at the Court of Appeals for the Federal Circuit (Case No. 23-1708). The appeal was filed on 6 April 2023, arising from an invalidity/cancellation action at the underlying proceeding. Fish & Richardson LLP represented Infineon; Heim, Payne & Chorush, LLP acted for Arigna.

The appeal was terminated on 28 October 2024 by a consent order dismissing the case under Fed. R. App. P. 42(b), with each party to bear its own costs. Rule 42(b) dismissals at the Federal Circuit require the parties’ agreement and the court’s approval; the absence of a cost award to either side suggests a negotiated resolution rather than a capitulation by one party. No merits ruling was issued, meaning the underlying patentability determination was not affirmed, reversed, or vacated by the Federal Circuit.

At 571 days, the appeal ran for nearly 16 months before resolution — consistent with a timeline in which briefing was substantially advanced or settlement negotiations were protracted before a mutual agreement was reached. The public record does not disclose whether a licensing arrangement, cross-licence, or other commercial deal accompanied the dismissal. The fate of the underlying invalidity/cancellation finding remains the operative legal status of US8247867B2, since no appellate merits decision was rendered.

Case at a glance
Case no.23-1708
CourtCourt of Appeals for the Federal Circuit
JudgeN/A
FiledApril 6, 2023
ClosedOctober 28, 2024
Duration571 days
OutcomeVoluntary dismissal
Verdict causePatentability
BasisVoluntary dismissal
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Case timeline

Filing to Voluntary dismissal in 571 days

571 days from filing to dismissal — longer than the median Federal Circuit appeal resolution

Case timeline: Appeal filed APR 6 2023, JAN–FEB — 571 days total Horizontal timeline showing the three key events in Infineon Technologies, AG v Arigna Technology, Ltd. from filing to resolution. Source: PACER, Court of Appeals for the Federal Circuit. APR 6 2023 Appeal filed Pre-trial proceedings OCT 28 2024 Voluntary dismissal 571 DAYS TOTAL
Dismissal terms

Appeal dismissed by agreement: what FRAP 42(b) means for both parties

Legal mechanism

FRAP 42(b): a procedural exit with no merits ruling

Fed. R. App. P. 42(b) allows parties to dismiss an appeal by stipulation with court approval. Critically, the Federal Circuit issues no opinion on the underlying patentability question — the appeal simply ceases. This means neither party secured an appellate ruling validating or invalidating US8247867B2. The underlying PTAB or district court outcome, whatever it was, remains the last substantive word on the patent’s validity.

No merits adjudication
Appellant outcome

Infineon exits without an appellate win — or loss

As appellant, Infineon had sought reversal or vacatur of the underlying patentability ruling. By agreeing to dismiss under FRAP 42(b), Infineon forgoes any chance of an appellate ruling in its favour on US8247867B2. Whether this reflects a commercial settlement, a strategic portfolio decision, or changed business priorities is not discernible from the public record. The each-side-bears-costs structure suggests neither party extracted a financial concession on costs.

Appeal withdrawn by agreement
Appellee outcome

Arigna avoids a potential reversal — but no appellate validation either

Arigna Technology, as appellee defending the underlying invalidity/cancellation finding, avoids the risk that the Federal Circuit would have reversed or modified that outcome. However, Arigna also received no appellate endorsement of its position. The dismissal is neutral on the merits. For an IP licensing entity, the commercial calculus of settling versus obtaining a final appellate ruling likely drove the decision to agree to dismissal.

No appellate endorsement secured
Commercial implications

Patent’s enforceability status left unresolved at appellate level

Third parties assessing freedom to operate around US8247867B2 must look to the underlying proceeding outcome, not a Federal Circuit merits ruling, to understand the patent’s current validity status. The semiconductor device space sees frequent PTAB validity challenges; a FRAP 42(b) dismissal without merits ruling leaves commercial uncertainty intact. Competitors and licensees should conduct independent FTO analysis rather than relying on an appellate determination that was never made.

FTO analysis still required
Legal analysis based on PACER docket records for case 23-1708 and PatSnap Eureka litigation intelligence Search PatSnap Eureka ↗
Parties and representation

Full party and counsel information

RoleNameTypeDetail
PlaintiffInfineon Technologies, AGCompanyGlobal semiconductor manufacturer — holder of US8247867B2 (semiconductor device)Search in Eureka ↗
DefendantArigna Technology, Ltd.CompanyArigna Technology Ltd. — IP licensing entity asserting invalidity/cancellation of the patentSearch in Eureka ↗
Plaintiff counselDavid M. Hoffman CounselAttorneyCounsel for Infineon Technologies, AGSearch in Eureka ↗
Plaintiff counselKenneth Wayne DarbyAttorneyCounsel for Infineon Technologies, AGSearch in Eureka ↗
Plaintiff counselMichael John BallancoAttorneyCounsel for Infineon Technologies, AGSearch in Eureka ↗
Plaintiff counselShawn BastaniAttorneyCounsel for Infineon Technologies, AGSearch in Eureka ↗
Plaintiff law firmFish & Richardson LLPLaw FirmRepresenting Infineon Technologies, AGSearch in Eureka ↗
Defendant counselChristopher LimbacherAttorneyCounsel for Arigna Technology, Ltd.Search in Eureka ↗
Defendant counselMichael F. HeimAttorneyCounsel for Arigna Technology, Ltd.Search in Eureka ↗
Defendant counselRussell ChorushAttorneyCounsel for Arigna Technology, Ltd.Search in Eureka ↗
Defendant law firmHeim, Payne & Chorush, LLPLaw FirmRepresenting Arigna Technology, Ltd.Search in Eureka ↗
Presiding judgeJudge N/AJudgeCourt of Appeals for the Federal CircuitSearch in Eureka ↗
Official verdict

Official order — verbatim text

“The parties, having so agreed, IT IS ORDERED THAT: The above-captioned appeal is dismissed under Fed. R. App. P. 42(b) with each side to bear their own costs.”
Source: PACER Docket, Case 23-1708, Court of Appeals for the Federal Circuit

The dismissal order is minimalist by design: it records the parties’ agreement, invokes FRAP 42(b), and imposes no cost award. The absence of any merits language means the Federal Circuit expressed no view on the patentability of US8247867B2. For practitioners, the operative question is the precedential weight — or lack thereof — of the underlying invalidity/cancellation decision, which now stands unchallenged at the appellate level. The neutral cost allocation is consistent with a negotiated resolution rather than a default or abandonment.

PACER case 23-1708 · Public docket record Explore in Eureka ↗
Patent at issue

US8247867B2 — semiconductor device integrated circuit patent

Publication No.US8247867B2
Application No.US12/836922
Patent details
ProductSemiconductor device integrated circuit architecture
Cited in actionApril 6, 2023

US8247867B2, filed under application number US12/836922, covers semiconductor device technology — a domain central to integrated circuit design and manufacture. The patent’s claims are directed to structural or functional aspects of semiconductor devices, placing it squarely within the competitive core of the global chip industry. Its patentability was formally contested via an invalidity/cancellation action, reflecting the high-stakes nature of foundational semiconductor IP in the current litigation environment.

For a company of Infineon’s scale — a top-ten global semiconductor supplier — patents covering device architecture carry significant defensive and offensive value. An invalidity challenge by an IP licensing entity such as Arigna Technology signals that the claims of US8247867B2 were viewed as commercially significant enough to contest, and that third parties perceived potential exposure or licensing leverage. The unresolved appellate posture means the patent’s enforceability remains a live commercial question for the semiconductor industry.

Patent data sourced from USPTO via PatSnap Eureka patent database Search patent records in Eureka ↗
Freedom to operate

Should you run an FTO analysis against US8247867B2?

Any company designing, manufacturing, or commercialising semiconductor devices — including integrated circuit foundries, fabless chip designers, and automotive semiconductor suppliers — should assess exposure to US8247867B2. The appeal’s dismissal without a merits ruling means there is no Federal Circuit precedent clarifying the patent’s claim scope or validity. R&D and product teams working on device architectures covered by this patent family cannot rely on the dismissal as a clearance event.

PatSnap Eureka’s FTO Search Agent enables IP and engineering teams to map claim language from US8247867B2 against current product architectures, identify prior art cited in the underlying invalidity proceeding, and surface related family members or continuation patents that may carry similar claims. Given the unresolved validity status and the involvement of an IP licensing entity, a structured FTO review is a prudent step before committing to product designs in this space.

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Related litigation

Similar Federal Circuit semiconductor patent invalidity appeals

Related Federal Circuit appeals involving semiconductor device patent invalidity and cancellation actions, including comparable FRAP 42(b) dispositions and PTAB-originating disputes.

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Infineon Technologies, AG patent enforcement history, Court of Appeals for the Federal Circuit case history, Infineon Technologies, AG’s full IP portfolio, and comparable case analysis
Comparable PTAB appealsArigna v. semiconductor OEMsFRAP 42(b) dismissal patternsInfineon litigation history
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Strategic implications

What this case signals for the semiconductor patent IP landscape

A Federal Circuit appeal dismissed by stipulation in a semiconductor invalidity dispute carries distinct signals for patent holders and challengers alike.

FRAP 42(b) dismissals leave underlying validity status as the operative record

When a Federal Circuit appeal ends under Rule 42(b), the last substantive ruling — typically a PTAB final written decision or district court judgment — governs. IP teams monitoring US8247867B2 or structuring licences around semiconductor device patents should anchor their analysis to that underlying record, not assume the dismissal is a clean slate for either party.

Each-side-bears-costs orders signal negotiated exits, not unilateral capitulation

A mutual cost-bearing dismissal at the Federal Circuit level typically suggests the parties reached a negotiated resolution — whether commercial, licensing-based, or strategic — rather than one side simply giving up. For in-house IP teams, this pattern suggests that monitoring settlement signals in advanced-stage Federal Circuit appeals can surface licensing opportunities or litigation risk earlier than waiting for a merits ruling.

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Settlement leverage signalsSemiconductor FTO exposureArigna IP portfolio risk
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Frequently asked questions

Infineon v Arigna — key questions answered

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Monitor semiconductor patent validity and FTO risk with PatSnap

US8247867B2 carries no Federal Circuit merits ruling — making independent FTO analysis essential for any team working in semiconductor device design. PatSnap Eureka tracks claim scope, family members, and new invalidity challenges in real time.

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