Infringement action filed 8 May 2019 in the United States District Court for the District of Delaware and closed 11 Sep 2023, with 5 patents asserted. Recorded basis of termination: dismissed with prejudice.
Comprise BGA solder balls arranged on a bottom surface of the lower insulating layer, which are used for soldering when mounting the package to a circuit board · Comprise a BGA substrate including an upper insulating layer comprising a plurality of laminated layers, an intermediate insulating layer, and a lower insulating layer comprising a plurality of laminated insulating layers · 16nm Pascal GPUs · 28nm Kepler GPUs · 28nm Maxwell GPUs · 28nm Tegra K1 SoCs · 40nm Fermi GPUs · NVIDIA’s20nm Tegra X1 SoCs
Source: Patsnap Litigation Data. Case 1:19-cv-00861, United States District Court for the District of Delaware.Open this record in Eureka
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The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.
4 on recordIPR2020-01735 · filed by Semiconductor Components Industries, LLC dba ON SemiconductorIPR2017-00107 · Other · filed by Broadcom LimitedIPR2020-00602 · Patentability · filed by Nvidia Corp.IPR2018-01402 · Other · filed by SAMSUNG ELECTRONICS CO., LTD.
A semiconductor apparatus that allow miniaturization of a multichip module using an interposer substrate and a method of manufacturing the same are provided. It is configured that an embedded electrode (4) penetrating through an interposer substrate (1) is provided, one end thereof is made to be connected to a connection electrode (2) on which device chips (10) are flip-chip mounted, and connecting to an unillustrated mounting substrate via a bump electrode (5), that is, because an electrode connecting the mounting substrate is made to be drawn out from the back surface of the interposer substrate (1), a multichip module can be miniaturized.
The docket lists 5 asserted patents. Full bibliographic detail, drawings and prosecution history for the remaining 3 asserted patents are one query away in Eureka.
Brian E. Farnan · Laura E. Muschamp · Matthew Phelps · Michael E. Bowlus · Michael J. Farnan · Michael K. Plimack · Nitin Subhedar · Robert E. Freitas · Sylvia Huang · Thomas Garten · Udit Sood · Ziwei Song
Source: case record + Patsnap company data. Attorney names appear as recorded in the docket.Compare both portfolios
Outcome
Basis of termination
From the record · verbatim
"Plaintiffs Adeia Semiconductor Technologies LLC and Adeia Semiconductor Advanced Technologies Inc.1 (together, “Adeia”) and Defendant NVIDIA Corporation (“NVIDIA”) (collectively, the “Parties”), by and through their counsel, file this Stipulation of Dismissal of All Remaining Claims, and in support hereof state: 1. On May 8, 2019, Adeia filed a Complaint against NVIDIA alleging five counts of patent infringement. 2. On July 1, 2019, NVIDIA filed an Answer to the Complaint. (D.I. 8.) NVIDIA did not assert any counterclaims. 3. On May 5, 2020, at the request of the Parties, the Court ordered the dismissal of Count V of the Complaint with prejudice. (D.I. 143.) 4. On October 20, 2020, at the request of the Parties, the Court ordered the dismissal of Count IV of the Complaint with prejudice. (D.I. 199.) 1 Invensas Corporation is now known as Adeia Semiconductor Technologies LLC. See D.I. 205. Tessera Advanced Technologies, Inc. is now known as Adeia Semiconductor Advanced Technologies Inc. Id. Case 1:19-cv-00861-RGA Document 208 Filed 09/11/23 Page 1 of 2 PageID #: 7828 2 5. The Parties have settled any and all remaining claims for relief in this action, and wish to dismiss with prejudice the remaining claims for relief as set forth in Count I, Count II, and Count III of the Complaint. 6. The Parties agree that each party will bear its own costs and attorneys’ fees with regard to this action, including with respect to Count I, Count II, and Count III. WHEREFORE, the Parties hereby agree and stipulate that Count I, Count II, and Count III of the Complaint shall be dismissed with prejudice, each party to bear its own fees and costs."
Case 1:19-cv-00861 · D. Del. · closed 11 September 2023
Source: case record, verbatim. The quoted paragraph is the basis-of-termination text as filed.
Related cases
Three questions this record usually leads to. Each one runs against the full litigation and patent corpus, and cites what it finds.
1:19-cv-00861 is a patent infringement action brought by Invensas, Corp. against Nvidia, Corp., filed on 8 May 2019 in the United States District Court for the District of Delaware. The case closed on 11 September 2023.
Which patents were asserted in 1:19-cv-00861?
US6849946B2 (“Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect”), assigned to INVENSAS CORPORATION, currently inactive; US7064005B2 (“Semiconductor apparatus and method of manufacturing same”), assigned to TESSERA ADVANCED TECHNOLOGIES, INC., currently inactive; US6317333B1 (“Package construction of semiconductor device”), assigned to TESSERA ADVANCED TECHNOLOGIES, INC.; US6232231B1 (“Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect”), assigned to INVENSAS CORPORATION; US5666046A (“Reference voltage circuit having a substantially zero temperature coefficient”), assigned to TESSERA ADVANCED TECHNOLOGIES, INC.. The record also lists Comprise BGA solder balls arranged on a bottom surface of the lower insulating layer, which are used for soldering when mounting the package to a circuit board, Comprise a BGA substrate including an upper insulating layer comprising a plurality of laminated layers, an intermediate insulating layer, and a lower insulating layer comprising a plurality of laminated insulating layers, 16nm Pascal GPUs, 28nm Kepler GPUs, 28nm Maxwell GPUs, 28nm Tegra K1 SoCs, 40nm Fermi GPUs and NVIDIA’s20nm Tegra X1 SoCs.
How was case 1:19-cv-00861 terminated?
The recorded basis of termination is dismissed with prejudice. The termination text reads: "Plaintiffs Adeia Semiconductor Technologies LLC and Adeia Semiconductor Advanced Technologies Inc.1 (together, “Adeia”) and Defendant NVIDIA Corporation (“NVIDIA”) (collectively, the “Parties”), by and through their counsel, file this Stipulation of Dismissal of All Remaining Claims, and in support hereof state: 1. On May 8, 2019, Adeia filed a Complaint against NVIDIA alleging five counts of patent infringement. 2. On July 1, 2019, NVIDIA filed an Answer to the Complaint. (D.I. 8.) NVIDIA did not assert any counterclaims. 3. On May 5, 2020, at the request of the Parties, the Court order
What does dismissal with prejudice mean?
A dismissal with prejudice permanently ends the claims that were filed, so the same claims cannot be brought again against that defendant. It is the usual form when the parties have settled.
How long did case 1:19-cv-00861 take?
1587 calendar days, from filing on 8 May 2019 to closure on 11 September 2023.
Who were the attorneys and the judge in 1:19-cv-00861?
Chief Judge Richard G. Andrews presided. Brian E. Farnan, Laura E. Muschamp, Matthew Phelps, Michael E. Bowlus, Michael J. Farnan, Michael K. Plimack, Nitin Subhedar, Robert E. Freitas, Sylvia Huang, Thomas Garten, Udit Sood and Ziwei Song are recorded as counsel for plaintiff Invensas. Alan Limbach, Asa Wynn-Grant, Brian A. Biggs, Carrie L. Williamson, Clayton Thompson, Denise Seastone Kraft, Erin E. Larson, Mark Fowler, Monica De Lazzari, Sangwon Sung and Saori Kaji appear for defendant Nvidia.
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