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Invensas & Tessera v. NVIDIA – Semiconductor Packaging IP Dispute | PatSnap
Patent Litigation

Invensas & Tessera v. NVIDIA: Five-Patent Semiconductor Dispute Dismissed With Prejudice

Invensas Corp. and Tessera Advanced Technologies (now Adeia) filed suit against NVIDIA in Delaware in May 2019, asserting five patents covering BGA semiconductor packaging across GPU and SoC product lines including Pascal, Kepler, Maxwell, and Fermi architectures. After 1,587 days and sequential dismissal of two counts before settlement of the remaining three, the case closed in September 2023.

Resolution time
1587days
1,587 days from filing to final dismissal — over four years of active litigation in Delaware
Patents asserted
5
US6849946B2, US7064005B2, US6317333B1, US6232231B1, and US5666046A — five BGA semiconductor packaging patents asserted
Outcome
Dismissed with Prejudice
All five counts dismissed with prejudice; each party to bear its own costs and attorneys' fees
Cost ruling
Own Costs
Parties agreed each bears its own attorneys' fees and costs across all counts
Published by PatSnap Insights Team · Verified by PatSnap Eureka Data
Case overview

Four-Year Packaging IP Battle: Adeia and NVIDIA Settle All Claims

Invensas Corp. and Tessera Advanced Technologies, Inc. — both later rebranded as Adeia entities — filed a five-count patent infringement complaint against NVIDIA Corporation in the District of Delaware on May 8, 2019. The asserted patents (US6849946B2, US7064005B2, US6317333B1, US6232231B1, and US5666046A) relate to BGA semiconductor packaging technology. The accused products span multiple generations of NVIDIA GPUs and SoCs, including Pascal, Kepler, Maxwell, and Fermi GPU lines and Tegra K1 and Tegra X1 SoCs.

The case wound down in stages. Count V was dismissed with prejudice in May 2020 and Count IV in October 2020, both at the parties' joint request. The three remaining counts — Counts I, II, and III — were resolved through settlement, with a stipulation of dismissal with prejudice filed September 11, 2023. The parties agreed that each side would bear its own costs and attorneys' fees in full. The recorded basis of termination is 'Dismissed with Prejudice'; the docket order is styled as a Stipulation of Dismissal of All Remaining Claims filed jointly by the parties.

The case spanned more than four years, suggesting protracted negotiations across multiple claim subsets rather than a single global resolution. The sequential dismissal of two counts in 2020 before a final settlement in 2023 is consistent with a phased licensing or narrowing strategy, though the specific terms of any underlying agreement are not disclosed in the available record. NVIDIA filed no counterclaims, which may have narrowed the dispute's complexity on the defensive side.

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Case at a glance
DefendantNvidia, Corp.
CourtDelaware District Court
JudgeRichard G. Andrews
FiledMay 8, 2019
ClosedSeptember 11, 2023
Duration1587 days
OutcomeDismissed with Prejudice
Verdict causeInfringement Action
BasisDismissed with Prejudice
Prior Art Intelligence
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Case data sourced from PACER / Delaware District Court via PatSnap Eureka Litigation Intelligence Explore similar cases ↗
Case timeline

Filing to Dismissed with Prejudice in 1587 days

1,587 days from filing to final dismissal — over four years of active litigation in Delaware

Case timeline: Complaint filed MAY 8 2019 — 1587 days total Horizontal timeline showing the three key events in Invensas, Corp. v Nvidia, Corp. from filing to resolution. Source: PACER, Delaware District Court. MAY 8 2019 Complaint filed Pre-trial proceedings SEP 11 2023 Dismissed with Prejudice 1587 DAYS TOTAL
Patent at issue

US6849946B2 and four further patents — BGA semiconductor packaging technology

Publication No.US6849946B2
Application No.US09/779123
Patent details
ProductBGA semiconductor packaging with solder ball interconnects for IC mounting
Cited in actionMay 8, 2019

Publication No.US7064005B2
Application No.US10/474863
Patent details
ProductBGA substrate laminated insulating layer semiconductor packaging
Cited in actionMay 8, 2019

Publication No.US6317333B1
Application No.US09/427583
Patent details
ProductSemiconductor packaging interconnect structures
Cited in actionMay 8, 2019

Publication No.US6232231B1
Application No.US09/143723
Patent details
ProductSemiconductor packaging and substrate fabrication methods
Cited in actionMay 8, 2019

Publication No.US5666046A
Application No.US08/518768
Patent details
ProductSemiconductor packaging and bonding wire structures
Cited in actionMay 8, 2019
Technical brief · sourced from PatSnap patent database
Patent figurePatent figure
Representative claim (1 of 3 independent)
1. A method, comprising: etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench; filling said trenches with a conductive material; and polishing said conductive material to form dummy conductors in said laterally spaced dummy trenches and interconnect in said series of second trenches and said first trench, wherein said polishing comprises applying a liquid substantailly free of particulate matter between an abrasive polishing surface and the conduct…
Technical background
BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to integrated circuit manufacturing and, more particularly, to a substantially planarized interconnect topography and method for making spaced interconnect by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect structure and a series of relatively narrow interconnect structures. 2. Description of the Related Art Fabrication of an integrated circuit involves numerous processing steps. After imp…
Patent family
4 family members across 2 jurisdictions (TW, US)
PatSnap Eureka · FTO Search Agent
Should you run an FTO against US6849946B2 and the Adeia BGA portfolio?

Any company designing, manufacturing, or sourcing GPU, SoC, or high-performance compute packages using BGA substrates should assess exposure to these five patents. The accused products in this case spanned multiple process nodes and GPU generations, indicating the patents are not limited to a single architecture or technology node. Substrate manufacturers, ODMs, and fabless chip designers supplying BGA-packaged products into the US market face the highest risk profile.

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Official verdict

Official order — verbatim text

Plaintiffs Adeia Semiconductor Technologies LLC and Adeia Semiconductor Advanced Technologies Inc.1 (together, “Adeia”) and Defendant NVIDIA Corporation (“NVIDIA”) (collectively, the “Parties”), by and through their counsel, file this Stipulation of Dismissal of All Remaining Claims, and in support hereof state: 1. On May 8, 2019, Adeia filed a Complaint against NVIDIA alleging five counts of patent infringement. 2. On July 1, 2019, NVIDIA filed an Answer to the Complaint. (D.I. 8.) NVIDIA did not assert any counterclaims. 3. On May 5, 2020, at the request of the Parties, the Court ordered the dismissal of Count V of the Complaint with prejudice. (D.I. 143.) 4. On October 20, 2020, at the request of the Parties, the Court ordered the dismissal of Count IV of the Complaint with prejudice. (D.I. 199.) 1 Invensas Corporation is now known as Adeia Semiconductor Technologies LLC. See D.I. 205. Tessera Advanced Technologies, Inc. is now known as Adeia Semiconductor Advanced Technologies Inc. Id. Case 1:19-cv-00861-RGA Document 208 Filed 09/11/23 Page 1 of 2 PageID #: 7828 2 5. The Parties have settled any and all remaining claims for relief in this action, and wish to dismiss with prejudice the remaining claims for relief as set forth in Count I, Count II, and Count III of the Complaint. 6. The Parties agree that each party will bear its own costs and attorneys’ fees with regard to this action, including with respect to Count I, Count II, and Count III. WHEREFORE, the Parties hereby agree and stipulate that Count I, Count II, and Count III of the Complaint shall be dismissed with prejudice, each party to bear its own fees and costs.
Source: PACER Docket, Case 1:19-cv-00861, Delaware District Court

The stipulation of dismissal records that the parties settled all remaining claims and agreed to dismiss Counts I, II, and III with prejudice, with each party bearing its own costs and fees. This phrasing confirms the matter is permanently closed on these patents as between Adeia and NVIDIA, but discloses no financial terms, royalty arrangements, or licensing scope. The public record is silent on the specific terms of the underlying settlement.

PACER case 1:19-cv-00861 · Public docket record Explore in Eureka ↗
Dismissal terms

Dismissed with prejudice: what the resolution means for both parties

Legal mechanism

Stipulated dismissal with prejudice ends all five counts permanently

A dismissal with prejudice is a final adjudication on the merits — Adeia cannot re-file the same claims against NVIDIA on these five patents. The parties jointly filed a stipulation of dismissal covering the three remaining counts (I, II, III), following earlier court-ordered dismissals of Counts IV and V in 2020. No court-entered judgment on the merits was issued; the case closed by mutual agreement formalised through the stipulation.

Permanent bar on re-filing
Patent holder outcome

Adeia's claims are extinguished — no re-assertion on these patents against NVIDIA

As the dismissal is with prejudice, Adeia (formerly Invensas and Tessera) cannot pursue NVIDIA again on these five patents for the accused product generations. The parties settled the remaining claims, but the specific financial or licensing terms of that settlement are not disclosed in the available record. Adeia retains the underlying patents and may assert them against other parties.

Claims extinguished vs. NVIDIA
Defendant outcome

NVIDIA secures finality on BGA packaging claims without counterclaim exposure

NVIDIA filed no counterclaims upon answering the complaint, limiting its defensive exposure to the five asserted patents. The with-prejudice dismissal closes the litigation permanently on these patents. Each party bears its own costs and fees, meaning NVIDIA faces no awarded damages or fee-shifting. The specific terms of the settlement — including any licensing arrangements — are not disclosed in the public record.

No damages awarded on record
Commercial implications

BGA packaging IP remains a live risk for GPU and SoC supply chains

The Adeia portfolio covers foundational BGA semiconductor packaging techniques relevant across the GPU and SoC ecosystem. A settlement resolving claims against NVIDIA does not extinguish risks for other chip designers, board manufacturers, or ODMs using similar packaging architectures. Companies operating in 16nm–40nm process nodes with BGA substrates should assess exposure to the five asserted patents, which remain in force against third parties.

Live risk for third parties
Legal analysis based on PACER docket records for case 1:19-cv-00861 and PatSnap Eureka litigation intelligence Search PatSnap Eureka ↗
Parties and representation

Full party and counsel information

RoleNameTypeDetail
PlaintiffInvensas, Corp.Company/Search in Eureka ↗
Co-PlaintiffTessera Advanced Technologies, Inc.CompanySearch in Eureka ↗
DefendantNvidia, Corp.Company/Search in Eureka ↗
Plaintiff counselBrian E. FarnanAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselLaura E. MuschampAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselMatthew PhelpsAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselMichael E. BowlusAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselMichael J. FarnanAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselMichael K. PlimackAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselNitin SubhedarAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselRobert E. FreitasAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselSylvia HuangAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselThomas GartenAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselUdit SoodAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff counselZiwei SongAttorneyCounsel for Invensas, Corp.Search in Eureka ↗
Plaintiff law firmFarnan LLPLaw FirmRepresenting Invensas, Corp.Search in Eureka ↗
Defendant counselAlan LimbachAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselAsa Wynn-GrantAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselBrian A. BiggsAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselCarrie L. WilliamsonAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselClayton ThompsonAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselDenise Seastone KraftAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselErin E. LarsonAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselMark FowlerAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselMonica De LazzariAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselSangwon SungAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant counselSaori KajiAttorneyCounsel for Nvidia, Corp.Search in Eureka ↗
Defendant law firmBarnard, Mezzanotte, Pinnie, Seelaus & Kraft, LLPLaw FirmRepresenting Nvidia, Corp.Search in Eureka ↗
Defendant law firmDLA Piper LLPLaw FirmRepresenting Nvidia, Corp.Search in Eureka ↗
Presiding judgeJudge Richard G. AndrewsJudgeDelaware District CourtSearch in Eureka ↗
R&D signals

R&D signals in the BGA semiconductor packaging IP space

Patent and innovation intelligence derived from the Adeia vs. NVIDIA dispute — tracking portfolio activity, technology trends, and white-space opportunities in semiconductor packaging.

Patent portfolio

Adeia's BGA packaging portfolio extends well beyond these five patents

Invensas and Tessera — now consolidated under Adeia — have historically maintained large semiconductor packaging patent portfolios with significant continuation and divisional filing activity. R&D teams and IP counsel should map the full Adeia portfolio in BGA substrate and interconnect technology to identify which claim families remain active and which product categories are most exposed beyond the GPU segment.

Adeia portfolio breadth
Technology landscape

Advanced packaging filings are accelerating as chiplet and 2.5D/3D adoption grows

BGA packaging patents asserted against NVIDIA's GPU generations reflect a broader IP landscape that is rapidly expanding as chiplet architectures, 2.5D interposers, and 3D stacking gain commercial traction. Filing activity in advanced semiconductor packaging — including through-silicon vias, fan-out wafer-level packaging, and hybrid bonding — has grown substantially, signalling a new wave of IP risk for product teams designing next-generation compute packages.

Advanced packaging IP trend
Competitive IP posture

NVIDIA's own packaging IP filings reflect growing in-house innovation in substrate design

NVIDIA has expanded its own patent filing activity in packaging-adjacent domains, including interposer design, thermal management for GPU packages, and high-bandwidth memory integration. Mapping NVIDIA's internal packaging IP portfolio reveals both defensive depth and potential cross-licensing leverage in future disputes with packaging IP licensors. R&D teams benchmarking against NVIDIA should track continuation filings in this area.

NVIDIA packaging IP depth
White-space opportunity

White space remains in next-gen BGA substrate innovations for AI accelerator packaging

While legacy BGA patents cover foundational interconnect structures, the specific packaging requirements of large-die AI accelerators — including co-packaged optics, embedded power delivery, and ultra-dense solder ball arrays — remain areas of active filing with identifiable white space. Companies investing in novel substrate materials or fine-pitch BGA variants for AI compute may find patentable differentiation outside existing Adeia claim coverage.

AI accelerator packaging IP gap
Related litigation

Similar BGA semiconductor packaging patent disputes in Delaware District Court

Explore related patent infringement cases involving BGA semiconductor packaging technology and semiconductor IP licensing enforcement filed in Delaware District Court.

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Adeia v. other GPU makersBGA packaging disputes DETessera/Invensas case historySemiconductor packaging IPR filings
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Strategic implications

What this case signals for the semiconductor packaging IP landscape

A four-year, five-patent dispute against one of the world's largest GPU designers confirms that BGA packaging IP carries real enforcement weight.

Phased dismissals suggest a complex, iterative negotiation with NVIDIA

Two of five counts were dropped in 2020 — before the bulk of discovery — and the remaining three settled three years later. This pattern is consistent with a licensing negotiation that narrowed scope over time rather than a single deal. IP teams monitoring Adeia enforcement activity should model multi-year timelines when assessing dispute exposure.

No counterclaims from NVIDIA is a notable strategic data point

NVIDIA's decision not to assert counterclaims — including no invalidity challenges pursued as counterclaims in this suit — may reflect confidence in a negotiated resolution or a calculated avoidance of jury risk on validity. It limits the public record on whether these patents are vulnerably invalid, leaving their enforceability intact for future targets.

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Full strategic analysis in PatSnap Eureka
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Adeia portfolio exposure mapBGA licensing risk by nodeNVIDIA IP counter-strategy
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Frequently asked questions

Invensas v Nvidia — key questions answered

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PatSnap Eureka

Monitor Adeia's BGA packaging portfolio and protect your GPU products

Run a freedom-to-operate search across all five asserted Adeia patents in PatSnap Eureka before your next GPU or SoC tape-out. Set portfolio alerts on Adeia continuation filings to catch new claims before they reach the assertion stage.

Disclaimer

This page is compiled from public court dockets and third-party patent and litigation data via PatSnap Eureka, and is provided for general informational purposes only. The information shown — including party names, patent and application numbers, dates, case status, outcomes, and any analysis — may be incomplete, may not reflect the most recent filings or legal status, and may contain errors or omissions. Verify all details against official court records (for example, PACER) and the relevant patent office before relying on them.

Nothing on this page constitutes legal advice or a legal opinion on the validity, infringement, enforceability, or scope of any patent or case, and no attorney‑client relationship is created by its use. Any description of an outcome (such as a dismissal, settlement, or consent judgment) is a general summary, not a legal determination. All patents, trademarks, and company or law‑firm names are the property of their respective owners. PatSnap makes no warranty as to the accuracy or completeness of this content and disclaims, to the fullest extent permitted by law, all liability for reliance on it. For advice on a specific matter, consult qualified legal counsel.

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