Katana Silicon v. Micron: Federal Circuit Dismisses Semiconductor Patent Appeal
Katana Silicon Technologies brought an infringement appeal against Micron Technology and affiliated entities over three patents covering semiconductor device manufacturing and wiring substrate technologies. The Federal Circuit dismissed the appeal without reaching the merits, closing a 903-day proceeding that spanned from June 2023 to December 2025.
Federal Circuit Ends Katana–Micron Semiconductor Dispute on Procedural Grounds
Katana Silicon Technologies, LLC filed its appeal at the U.S. Court of Appeals for the Federal Circuit on 29 June 2023, asserting infringement of three patents — USRE038806E, US6731013B2, and US6352879B1 — against Micron Technology, Inc. and related entities including Micron Semiconductor Products, Inc., Micron Technology Texas, LLC, and the State of Idaho. The asserted patents relate to semiconductor device manufacturing methods and wiring substrate architectures used in package-stack semiconductor devices.
The Federal Circuit dismissed the appeal on 18 December 2025, recording the basis of termination as ‘Appeal Dismissed.’ The court’s order states simply that the cause was considered and adjudged dismissed, without issuing a substantive ruling on patent infringement or validity. This procedural disposition means no appellate court has ruled on the underlying merits of Katana’s infringement claims, leaving those questions formally unresolved at this level.
A 903-day duration for an appeal that concludes in dismissal rather than a merits decision is notable and may suggest jurisdictional, standing, or procedural deficiencies that prevented the court from reaching substance. The public record does not disclose the precise ground for dismissal, so the driving cause — whether jurisdictional defect, mootness, or a procedural filing issue — remains unknown from publicly available materials. Katana’s strategic options following this dismissal will depend on whether the dismissal forecloses refiling or leaves alternative paths open.
Filing to Appeal Dismissed in 903 days
903 days from filing to dismissal — above the median for Federal Circuit patent appeals
Appeal dismissed without merits: what the Federal Circuit’s order means
Procedural dismissal — no merits adjudication
A Federal Circuit dismissal of an appeal on procedural grounds means the court declined or was unable to reach the substance of the infringement and validity arguments. The order ‘DISMISSED’ does not constitute a ruling in favour of either party on the patent merits. Grounds for such dismissals typically include lack of appellate jurisdiction, mootness, standing defects, or failure to comply with procedural requirements — though the specific basis is not disclosed in the public record here.
No merits ruling issuedKatana’s infringement claims remain unresolved on appeal
For Katana Silicon Technologies, a dismissal without a merits ruling means its infringement allegations were never adjudicated at the Federal Circuit. Depending on the dismissal’s basis, Katana may or may not be able to refile or pursue alternative enforcement routes. If the dismissal was jurisdictional or procedural rather than substantive, the patents themselves remain technically enforceable — though further litigation would require overcoming whatever deficiency led to dismissal. The public record does not specify whether refiling is barred.
Patents not invalidatedMicron avoids a merits ruling — exposure persists in theory
Micron Technology and its affiliates secured dismissal of the appeal without any judicial finding of infringement — a commercially favourable outcome. However, because the dismissal appears procedural rather than substantive, there is no holding that Micron’s products do not infringe the asserted patents. Should Katana cure any procedural defect and refile, Micron could face renewed exposure. A full invalidity or non-infringement determination would provide stronger protection.
No infringement findingSemiconductor packaging IP landscape remains unsettled
Because the Federal Circuit issued no merits ruling, the three asserted patents covering semiconductor device manufacturing and wiring substrate technology retain their face validity. Companies operating in advanced packaging, stacked-die, and substrate interconnect segments — including Micron’s competitors — cannot rely on this dismissal as precedent that the patents are invalid or unenforceable. The uncertainty created by an unresolved procedural dismissal typically elevates FTO risk for the relevant technology class until the patents expire or are separately challenged.
IP uncertainty persistsFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Katana Silicon Technologies, LLC | Company | Patent assertion entity — holder of semiconductor device and wiring substrate patents including USRE038806ESearch in Eureka ↗ |
| Defendant | Micron Technology, Inc. | Company | Micron Technology, Inc. — global DRAM, NAND, and semiconductor memory manufacturer headquartered in Boise, IdahoSearch in Eureka ↗ |
| Co-Defendant | State of Idaho | Individual | Search in Eureka ↗ |
| Co-Defendant | Micron Semiconductor Products, Inc. | Company | Search in Eureka ↗ |
| Co-Defendant | Micron Technology Texas, LLC | Company | Search in Eureka ↗ |
| Plaintiff counsel | Joshua Bennett | Attorney | Counsel for Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Omer Salik | Attorney | Counsel for Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Scott W. Breedlove | Attorney | Counsel for Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Theresa Dawson | Attorney | Counsel for Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Baker & Hostetler LLP | Law Firm | Representing Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Carter Arnett PLLC | Law Firm | Representing Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Plaintiff law firm | Keker, Van Nest & Peters LLP | Law Firm | Representing Katana Silicon Technologies, LLCSearch in Eureka ↗ |
| Defendant counsel | Amanda Tessar | Attorney | Counsel for Micron Technology, Inc.Search in Eureka ↗ |
| Defendant counsel | Andrew Dufresne | Attorney | Counsel for Micron Technology, Inc.Search in Eureka ↗ |
| Defendant counsel | Jonathan Irvin Tietz | Attorney | Counsel for Micron Technology, Inc.Search in Eureka ↗ |
| Defendant law firm | Perkins Coie LLP | Law Firm | Representing Micron Technology, Inc.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Court of Appeals for the Federal CircuitSearch in Eureka ↗ |
Official order — verbatim text
The Federal Circuit’s order — ‘THIS CAUSE having been considered, it is ORDERED AND ADJUDGED: DISMISSED’ — is a terse procedural disposition that contains no substantive findings on patent infringement, claim construction, or validity. At the appellate level, such an order typically reflects a threshold defect that prevented merits review: possibilities include lack of appellate jurisdiction, mootness, or a sovereign immunity bar arising from the State of Idaho’s co-defendant status. Neither party received a ruling on the underlying merits of the semiconductor patent claims.
USRE038806E, US6731013B2 & US6352879B1 — Semiconductor Device and Wiring Substrate Patents
The three asserted patents span semiconductor device fabrication and substrate interconnect technology. USRE038806E is a reissue patent — a designation indicating the original patent was corrected through the USPTO reissue process to broaden or clarify claims after grant. US6731013B2 and US6352879B1 are utility patents covering wiring substrate architectures and semiconductor device packaging, including package-stack configurations. The application lineage traces to filings in the early 2000s, placing the inventions in the generation of packaging technology that preceded contemporary advanced packaging formats.
These patents sit in a commercially sensitive zone of semiconductor IP: substrate interconnect and package-stack technology underpin DRAM and NAND memory module assembly — core product lines for Micron. A reissue patent (USRE038806E) often signals that the patent holder broadened claims post-grant to capture commercial embodiments that emerged after original filing, which can increase infringement surface area. Companies in memory module assembly, advanced packaging, and chip-on-substrate manufacturing should monitor the status and claim scope of these patents, particularly if Katana pursues further enforcement action.
Should your team run an FTO against USRE038806E, US6731013B2, and US6352879B1?
Any organisation designing or manufacturing semiconductor devices using wiring substrate interconnects or package-stack architectures — including memory module assemblers, foundries, and OSAT providers — should assess freedom-to-operate against these three patents. The Federal Circuit’s procedural dismissal provides no infringement safe harbour. The reissue status of USRE038806E in particular warrants close claim-mapping, as reissued patents can carry broadened claims relative to the original grant.
PatSnap Eureka’s FTO Search Agent enables R&D and IP teams to map product architectures against the full claim scope of USRE038806E, US6731013B2, and US6352879B1 in minutes. The tool identifies claim language overlap, surfaces prior art that may support invalidity arguments, and tracks the prosecution history of reissue proceedings — giving your team the evidence base needed to make a defensible FTO determination before product launch or technology licensing decisions.
Run a freedom-to-operate analysis on USRE038806E to assess your product’s exposure
Run FTO in Eureka →Similar Federal Circuit Patent Appeals in Semiconductor Device Technology
Related Federal Circuit appeals involving semiconductor device, wiring substrate, and package-stack patents — including cases against major memory manufacturers.
What this case signals for the semiconductor packaging IP landscape
A procedural Federal Circuit dismissal leaves three semiconductor patents in legal limbo — with implications for anyone operating in advanced packaging.
Procedural dismissals do not extinguish patent risk
The Federal Circuit’s dismissal of Katana’s appeal on procedural grounds does not invalidate USRE038806E, US6731013B2, or US6352879B1. Companies designing or manufacturing semiconductor devices and package-stack substrates should not treat this outcome as a clearance. An FTO analysis against these patents remains relevant until they expire or are cancelled through IPR or ex parte reexamination.
Micron’s multi-entity structure complicates future enforcement targeting
Katana named Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas, LLC, and the State of Idaho as defendants — a structure consistent with patent assertion against a vertically integrated manufacturer with multiple operating subsidiaries. Future plaintiffs or Katana itself should expect jurisdictional complexity when naming state-affiliated entities, which may have introduced sovereign immunity issues that contributed to the dismissal.
Katana v Micron — key questions answered
Katana Silicon Technologies asserted three patents: USRE038806E (a reissue patent covering semiconductor device manufacturing), US6731013B2 (wiring substrate and semiconductor device), and US6352879B1 (semiconductor device and substrate fabrication). The products at issue relate to semiconductor device manufacturing methods and package-stack wiring substrate architectures.
The Federal Circuit’s order records only ‘Appeal Dismissed’ without specifying the ground. Possible bases include lack of appellate jurisdiction, mootness, or a sovereign immunity defence arising from the unusual inclusion of the State of Idaho as a named co-defendant. The public record does not disclose the precise reason, and no merits ruling was issued.
No. The dismissal is procedural and contains no substantive findings on infringement or patent validity. Neither party received a merits ruling. Micron was not adjudicated a non-infringer, and the asserted patents were not invalidated. The dismissal closes the appeal but does not resolve the underlying substantive dispute.
The State of Idaho’s involvement as a co-defendant is unusual and not explained in the publicly available case record. One possible explanation is that Idaho holds an ownership or licensing interest in certain Micron entities or facilities. Critically, U.S. states generally enjoy Eleventh Amendment sovereign immunity from patent infringement suits in federal court, which may have created a jurisdictional obstacle contributing to the appeal’s dismissal.
A reissue patent is granted by the USPTO when the original patent contained an error, including claims that were narrower than the inventor was entitled to. The reissue process can broaden claim scope relative to the original grant. USRE038806E’s reissue status means its claims may cover a wider range of commercial embodiments than the original patent, potentially increasing the infringement exposure for semiconductor device manufacturers and assemblers in the package-stack technology space.
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