Monterey Research v. STMicroelectronics: Memory Patent Dispute Ends in Dismissal
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📋 Case Summary
| Case Name | Monterey Research, LLC v. STMicroelectronics, Inc. |
| Case Number | 1:20-cv-00089 (D. Del.) |
| Court | U.S. District Court for the District of Delaware |
| Duration | Jan 2020 – Apr 2024 1,560 days (4.3 years) |
| Outcome | Defendant Win — Dismissal with Prejudice |
| Patents at Issue | |
| Accused Products | DDR3/DDR4 SDRAM-compliant devices, LPDDR3/LPDDR4 memory controllers, SRAM-integrated microcontrollers (SPC570S40E1), SPEAr300/310/320/320s/600, STA1295, SPC750S40E1 |
Case Overview
The Parties
⚖️ Plaintiff
A patent assertion entity (PAE) holding intellectual property assets originally developed in the semiconductor memory space.
🛡️ Defendant
The U.S. subsidiary of a global semiconductor leader with significant operations in automotive-grade microcontrollers, embedded processors, and memory-integrated system-on-chip (SoC) products.
Patents at Issue
This dispute centered on four U.S. patents covering semiconductor memory technologies, with claims spanning memory cell architecture, interface design, and semiconductor process technology:
- • US6459625B1 — Semiconductor memory technology
- • US6651134B1 — Memory architecture claims
- • US6534805B1 — Memory cell or interface technology
- • US7495951B1 — Memory-related semiconductor design
Developing memory products or integrated circuits?
Ensure your designs don’t infringe these or related patents. Early FTO is key.
The Verdict & Legal Analysis
Outcome
The case concluded with a **stipulated dismissal with prejudice** on April 29, 2024, pursuant to Federal Rule of Civil Procedure 41(a)(1)(A)(ii). Crucially, the dismissal stipulated that **each party bears its own attorneys’ fees and costs**, implying a negotiated resolution without public damages or a court ruling on the merits.
Key Legal Issues
The extended duration of the litigation (1,560 days) and its resolution via stipulated dismissal suggest several underlying dynamics. Semiconductor memory patent claims are highly technical, often leading to complex claim construction disputes. Given the accused products’ compliance with JEDEC standards (DDR3, DDR4, LPDDR3, LPDDR4), issues of standard-essentiality and design-around feasibility likely played a role. Furthermore, defendants frequently employ post-grant proceedings (IPR petitions) at the PTAB to challenge patent validity, which can significantly influence litigation posture. The mutual fee-bearing outcome points to neither party achieving a dominant litigation position after prolonged discovery and motion practice.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor memory and JEDEC-standard products. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation.
- View all 4 patents in this technology space
- See which companies are most active in memory patents
- Understand claim construction patterns for JEDEC standards
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High Risk Area
JEDEC-compliant DDR/LPDDR interfaces
4 Related Patents
In this specific litigation
Strategic Defenses
Can neutralize NPE assertion
✅ Key Takeaways
Rule 41(a)(1)(A)(ii) mutual dismissals with prejudice and self-bearing fee structures signal balanced litigation outcomes — neither side achieved dominant position after 1,560 days.
Search related case law →Multi-patent, multi-product semiconductor cases in Delaware routinely run 4+ years before resolution.
Explore precedents →Frequently Asked Questions
Four U.S. patents: US6459625B1, US6651134B1, US6534805B1, and US7495951B1, covering semiconductor memory architecture and interface technologies.
The parties filed a joint stipulation under FRCP 41(a)(1)(A)(ii), agreeing to dismiss all claims with each side bearing its own fees — indicating a negotiated resolution without judicial determination on the merits.
It confirms that JEDEC-standard memory products remain active NPE assertion targets; companies commercializing DDR4 or LPDDR4 devices should maintain proactive FTO analysis and IPR petition readiness.
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References
- PACER — Case No. 1:20-cv-00089, D. Del.
- USPTO Patent Center — Patent Details
- JEDEC Solid State Technology Association — Standards
- Cornell Legal Information Institute — Federal Rule of Civil Procedure 41
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.