Monterey Research v. Toshiba: Memory Patent Dispute Dismissed With Prejudice
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📋 Case Summary
| Case Name | Monterey Research, LLC v. Toshiba, Inc. |
| Case Number | 6:23-cv-00340 (W.D. Tex.) |
| Court | U.S. District Court for the Western District of Texas |
| Duration | May 9, 2023 – March 28, 2024 324 days |
| Outcome | Dismissed with Prejudice — Confidential Settlement |
| Patents at Issue | |
| Accused Products | Authenticated memory controllers, impedance-matched interface circuits, high-speed sense amplifiers, and secure memory management systems across Toshiba’s semiconductor and storage device lines. |
Case Overview
The Parties
⚖️ Plaintiff
Patent assertion entity that holds semiconductor and memory-related IP originally developed within the consumer electronics and chip design industries.
🛡️ Defendant
Global technology conglomerate and major semiconductor and data storage manufacturer with product lines spanning NAND flash memory and storage controllers.
Patents at Issue
This case involved six U.S. patents covering memory architecture, secure memory management, impedance matching, and current-sensing technologies — core building blocks of modern semiconductor and storage systems.
- • US7888962B1 — Authenticated memory and controller slave
- • US7405987B1 — Impedance matching circuit
- • US7979658B2 — Low voltage, high gain current/voltage sense amplifier with improved read access time
- • US9767303B2 — Secure management of memory regions in a memory
- • US7836269B2 — Systems and methods for access violation management of secured memory
- • US8694776B2 — (Memory security and architecture)
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The Verdict & Legal Analysis
Outcome
The case concluded with all claims and counterclaims dismissed with prejudice by the Western District of Texas. No damages amount was publicly disclosed, signaling a confidential settlement agreement. The resolution in just 324 days places this case in the accelerated resolution category for multi-patent district court litigation.
Key Legal Issues
The dismissal with prejudice applies bilaterally — extinguishing both Monterey Research’s infringement claims and Toshiba’s counterclaims (which typically include invalidity and non-infringement defenses). For patent attorneys, the absence of any claim construction order, Markman hearing record, or invalidity ruling means this case contributes no public precedent on the patentability or scope of the six asserted patents. These patents remain valid and unaddressed by a court on the merits, preserving Monterey Research’s ability to assert them against other defendants.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor memory design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation.
- View all 6 related patents in this technology space
- See which companies are most active in memory patents
- Understand claim construction patterns
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High Risk Area
Authenticated memory and secure partitioning
6 Related Patents
In memory security space
Design-Around Options
Available for many claims
✅ Key Takeaways
Bilateral dismissal with prejudice signals confidential settlement — no public claim construction or validity precedent was established.
Search related case law →Six-patent assertions against semiconductor defendants create asymmetric invalidity risk that accelerates settlement timelines.
Explore litigation strategies →Authenticated memory interfaces and secure memory partitioning are active litigation targets.
Start FTO analysis for my product →Design-around analysis for impedance matching circuits and sense amplifier architectures is advisable for new silicon designs.
Try AI patent drafting →Frequently Asked Questions
Six U.S. patents were asserted: US7888962B1, US7405987B1, US7979658B2, US9767303B2, US7836269B2, and US8694776B2 — covering authenticated memory, impedance matching, sense amplifiers, and secure memory management.
The bilateral dismissal with prejudice of all claims and counterclaims is consistent with a confidential settlement agreement. No financial terms were publicly disclosed.
The patents remain valid and unreviewed on the merits, preserving assertion potential against other defendants. Companies developing memory security and controller-slave interface technologies should treat these patents as active risks.
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PatSnap IP Intelligence Team
Patent Research & Competitive Intelligence · PatSnap
This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.
The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.
References
- USPTO Patent Full-Text Database (Google Patents)
- PACER Case Docket 6:23-cv-00340
- World Intellectual Property Organization
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.
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