MOSAID Technologies vs. Intel: Semiconductor Patent Case Transferred to Oregon

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📋 Case Summary

Case NameMOSAID Technologies, Inc. v. Intel Corp.
Case Number1:25-cv-00677 (WDTX), 3:26-cv-246 (D. Oregon)
CourtWestern District of Texas (transferred from) to District of Oregon
DurationMay 6, 2025 – Feb 3, 2026 273 days
OutcomeTransferred — Litigation Ongoing
Patents at Issue
Accused ProductsIntel’s 10nm, Intel 4, Intel 7, Intel 3, FinFET Low Power (22FFL), and Intel 16 process nodes

Case Overview

The Parties

⚖️ Plaintiff

MOSAID Technologies, Inc. is a well-established patent licensing and assertion entity with a substantial portfolio concentrated in semiconductor memory and logic technologies.

🛡️ Defendant

Intel Corporation is one of the world’s largest semiconductor manufacturers. Its advanced process nodes represent billions of dollars in R&D investment.

The Patents at Issue

MOSAID asserted 11 U.S. patents spanning semiconductor device architecture and fabrication. These patents generally cover transistor structures, semiconductor device configurations, and fabrication processes directly implicated by Intel’s FinFET-based manufacturing.

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Litigation Timeline & Legal Analysis

Litigation Timeline & Procedural History

MOSAID filed suit on May 6, 2025, in the Western District of Texas — a calculated choice. The WDTX, under Chief Judge Alan D. Albright, has been among the nation’s most active venues for patent litigation.

However, after 273 days — on February 3, 2026 — the case was formally transferred, with the docket officially received by the District of Oregon on February 5, 2026, as Case No. 3:26-cv-246. Judge Alan D. Albright, who presided during the WDTX phase, is one of the most prominent patent judges in the country — his docket management practices and claim construction approaches are closely followed by the patent bar. The case’s transfer out of his court is itself a strategically significant event worth monitoring.

Outcome

The Western District of Texas closed the case on February 3, 2026, with the formal basis of termination being the transfer to the District of Oregon (Case No. 3:26-cv-246). No final judgment on the merits, damages award, or injunctive relief was issued at this stage. The substantive infringement claims — covering 11 patents and six Intel process node families — remain actively pending before the Oregon court.

Venue Transfer Analysis

The transfer from WDTX to Oregon is the defining legal event of this case’s first phase. Intel’s primary operations and relevant R&D activities are headquartered in Santa Clara, California, with significant engineering presence in Oregon (notably, Intel’s Hillsboro campus is one of its largest fabrication and engineering sites). Under In re Apple and subsequent Federal Circuit venue jurisprudence, defendants have increasingly succeeded in transferring cases away from WDTX when key witnesses and evidence are located elsewhere.

For MOSAID, the WDTX filing was a deliberate venue strategy — one that has become more difficult to sustain post-In re Volkswagen and related transfer decisions that strengthened defendants’ ability to invoke § 1404(a). The transfer to Oregon places the case in a venue where Intel has substantial local presence, potentially shifting procedural dynamics in Intel’s favor.

Legal Significance

This case exemplifies the ongoing tension between patent assertion entities and venue selection strategy following the Federal Circuit’s tightening of WDTX transfer standards. The 273-day WDTX tenure — encompassing likely early motions, scheduling orders, and transfer briefing — consumed significant litigation resources without reaching merits adjudication.

With 11 patents at issue, claim construction proceedings in Oregon will be pivotal. The patents cover semiconductor structural and process technologies, meaning construction of terms like “transistor channel region,” “gate dielectric,” or “fin structure” could determine infringement across Intel’s entire advanced node lineup simultaneously.

Strategic Takeaways

For Patent Holders: MOSAID’s multi-patent, multi-product assertion strategy is high-leverage but venue-vulnerable. Patent holders targeting large semiconductor defendants should conduct rigorous § 1404(a) analysis before filing in WDTX, particularly when defendants have established engineering operations in other districts.

For Accused Infringers: Intel’s successful transfer (if transfer was defendant-initiated) demonstrates the ongoing value of venue challenges as a defensive tool. Early investment in transfer motions can reset the litigation dynamic and move cases to more favorable judicial environments.

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Industry & Competitive Implications

The MOSAID v. Intel dispute reflects a broader pattern of **semiconductor process node patent enforcement** that R&D and legal teams across the chip industry must monitor.

📋 MOSAID’s Portfolio Approach

MOSAID’s assertion of patents spanning multiple node generations (22FFL through Intel 3) suggests a portfolio theory of infringement: that core structural innovations persist across generational process improvements.

  • View all 11 asserted patents in detail
  • Analyze claim construction strategies
  • Understand portfolio assertion patterns
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High Risk Areas

FinFET structures, Gate-All-Around (GAA) transistors, interconnect architectures

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11 Patents at Issue

Covering multiple Intel process node generations

Venue Challenges

Crucial defensive tool for large defendants

✅ Key Takeaways

For Patent Attorneys

Venue selection in WDTX remains viable but requires rigorous § 1404(a) risk analysis when defendants have multi-state engineering operations.

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Multi-patent assertions against manufacturing processes require coordinated claim construction strategies.

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Transfer to defendant-friendly venues can reset case dynamics significantly.

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For IP Professionals

MOSAID’s portfolio approach — 11 patents across six product lines — reflects modern PAE assertion strategy targeting process-level technology.

Monitor PAE activity →

Monitor Case No. 3:26-cv-246 (D. Oregon) for claim construction orders with industry-wide implications.

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For R&D Leaders

Advanced node FTO analysis must extend beyond product patents to fabrication process and transistor structure IP.

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Enterprise-level patent risk management should include PAE portfolio monitoring in semiconductor domains.

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PatSnap IP Intelligence Team

Patent Research & Competitive Intelligence · PatSnap

This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.

The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.

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Related Resources

  1. USPTO Patent Full-Text Database — Search MOSAID patent numbers
  2. PACER Case Locator — Case Nos. 1:25-cv-00677 (WDTX) and 3:26-cv-246 (D. Oregon)
  3. Federal Circuit decisions on WDTX venue transfer standards — In re Apple, In re Volkswagen

This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.

⚖️ Disclaimer: This article is for informational purposes only and does not constitute legal advice. The analysis presented reflects publicly available case information and general legal principles. For specific advice regarding patent litigation, FTO analysis, or IP strategy, please consult a qualified patent attorney.