PACT XPP Schweiz v. Intel (25-1003): Federal Circuit Appeal Dismissed as Premature
PACT XPP Schweiz AG pursued Intel Corp. over 12 patents covering logic cell array and bus system technology. The Federal Circuit appeal was dismissed in 120 days after both parties jointly acknowledged it was filed prematurely — before resolution of pending counterclaims — leaving the door open for reinstatement.
A premature Federal Circuit appeal paused, not ended
PACT XPP Schweiz AG, a Swiss IP holding entity asserting a portfolio of reconfigurable processor and logic cell array patents, filed an appeal at the Court of Appeals for the Federal Circuit on 2 October 2024 against Intel Corp. (Case No. 25-1003). The appeal concerned an infringement action involving 12 US patents — including US8471593B2, US8312301B2, US8819505B2 and nine further patents — all directed at logic cell array and bus system technology. Intel was represented by Kirkland & Ellis LLP; PACT by Quinn Emanuel Urquhart & Sullivan LLP.
The appeal closed on 30 January 2025 when the Federal Circuit granted a joint motion to dismiss. Both parties agreed the appeal had been filed prematurely — before an order disposing of pending counterclaims had been entered, meaning no final, appealable judgment yet existed. The dismissal was conditional: PACT may reinstate the appeal under the same docket number, without paying additional filing fees, if it files a new notice of appeal within 60 days of entry of a final judgment in the underlying case. Each side bears its own costs.
The 120-day resolution is notable primarily because it reflects procedural rather than substantive resolution — the merits of infringement across all 12 patents remain unadjudicated at the appellate level. The premature filing suggests the underlying district court proceedings may still have open counterclaim issues that Intel pressed to conclusion. The 60-day reinstatement window means this appeal could revive rapidly once a final district court judgment issues, and the breadth of the 12-patent portfolio signals PACT’s enforcement strategy remains active.
Filing to Appeal Dismissed in 120 days
Resolved in 120 days — faster than typical Federal Circuit appeals, driven by procedural posture rather than merits.
Appeal dismissed as premature: what the conditional order means
Premature appeal: no final judgment, no jurisdiction
Federal circuit appellate jurisdiction typically requires a final judgment disposing of all claims. Because pending counterclaims remained unresolved in the underlying case, the Federal Circuit lacked jurisdiction to hear this appeal on the merits. Both parties conceded this, moving jointly for dismissal rather than litigating jurisdiction. The dismissal is procedural — it does not touch infringement liability or patent validity.
Procedural dismissal — no merits ruling60-day window to revive: PACT’s path back to appeal
The order preserves PACT’s appellate rights. If a final judgment issues in the district court within 60 days of this order, PACT may reinstate the appeal under docket 25-1003 without paying additional filing fees. This mechanism protects PACT from filing fee prejudice caused by the premature filing, while incentivising prompt resolution of the underlying counterclaims. If the 60-day window lapses, a new, separately numbered appeal would be required.
Reinstatement within 60 daysIntel co-operated on dismissal but the fight is not over
Intel’s agreement to joint dismissal is consistent with a tactical preference to fully resolve counterclaims at district level before appellate scrutiny. Pending counterclaims — which Intel presumably pressed — may serve to narrow, reframe or negate PACT’s infringement claims across the 12-patent portfolio. Intel’s cooperation here does not signal concession on the merits; it suggests confidence in the district court proceedings still underway.
Counterclaims still pending12 live patents: enforcement risk for logic cell array sector
PACT’s 12-patent portfolio spanning logic cell array, reconfigurable processor bus systems and related architectures remains enforceable. The dismissal changes nothing about validity or scope. Semiconductor and processor companies whose products intersect with programmable logic, FPGA-adjacent architectures, or reconfigurable computing bus designs should treat this case as dormant rather than resolved — a reinstated appeal could follow district court final judgment rapidly.
Portfolio still active — monitor closelyFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | PACT XPP Schweiz, AG | Company | Swiss IP holding entity — holder of 12 logic cell array and reconfigurable processor patentsSearch in Eureka ↗ |
| Defendant | Intel, Corp. | Company | Intel Corp. — global semiconductor and processor manufacturer (Kirkland & Ellis LLP)Search in Eureka ↗ |
| Plaintiff counsel | Frederick A. Lorig | Attorney | Counsel for PACT XPP Schweiz, AGSearch in Eureka ↗ |
| Plaintiff counsel | Mark YehKai Tung | Attorney | Counsel for PACT XPP Schweiz, AGSearch in Eureka ↗ |
| Plaintiff counsel | Quincy Lu Mr. | Attorney | Counsel for PACT XPP Schweiz, AGSearch in Eureka ↗ |
| Plaintiff counsel | Sanford Ian Weisburst | Attorney | Counsel for PACT XPP Schweiz, AGSearch in Eureka ↗ |
| Plaintiff law firm | Quinn Emanuel Urquhart & Sullivan, LLP | Law Firm | Representing PACT XPP Schweiz, AGSearch in Eureka ↗ |
| Defendant counsel | Brandon Brown | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Diva R. Hollis | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Greg Arovas | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Jason M. Wilcox | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | John C. O’Quinn | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Robert Alan Appleby | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Stephen DeSalvo AT | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | Todd M. Friedman | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant counsel | William H. Burgess | Attorney | Counsel for Intel, Corp.Search in Eureka ↗ |
| Defendant law firm | Kirkland & Ellis, LLP | Law Firm | Representing Intel, Corp.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | Court of Appeals for the Federal CircuitSearch in Eureka ↗ |
Official order — verbatim text
The Federal Circuit’s order is explicitly procedural: it confirms that both parties agreed the appeal was premature due to pending counterclaims in the underlying infringement action. No merits determination was made on any of the 12 asserted patents. The conditional reinstatement provision — same docket, no additional fee, 60-day window — is a practical accommodation that preserves PACT’s appellate rights without penalising the premature filing. The cost-splitting direction, while standard in joint dismissals, reflects the mutual acknowledgment of the procedural error rather than any substantive win or loss for either side.
US8471593B2 and 11 further patents — logic cell array and bus system architecture
The 12 patents asserted by PACT XPP Schweiz span a family of inventions directed at reconfigurable logic cell arrays, programmable bus systems, and processor interconnect architectures. Key patents such as US8471593B2 and US8312301B2 cover the structural and operational design of arrays of configurable logic cells that can be dynamically reconfigured for different computational tasks — a technology domain central to modern FPGA-adjacent and heterogeneous computing architectures. Application dates across the portfolio range from the mid-2000s to the early 2010s, reflecting a sustained filing programme.
PACT XPP’s reconfigurable processor IP has historically been asserted against major semiconductor companies, positioning this portfolio as a strategic enforcement asset in the high-performance computing and processor design space. For Intel — whose product lines include programmable logic devices, multi-core processors, and heterogeneous compute platforms — the breadth of 12 asserted patents creates significant claim-mapping exposure. Competitors and suppliers developing FPGA, CGRA (coarse-grained reconfigurable array), or advanced bus interconnect products should treat this portfolio as a material prior art and FTO risk reference point.
Should your team run an FTO against PACT XPP’s logic cell array portfolio?
Any company developing reconfigurable processor architectures, coarse-grained reconfigurable arrays (CGRAs), FPGA-adjacent designs, or programmable bus interconnect systems should assess freedom-to-operate against PACT XPP Schweiz’s 12-patent portfolio. With the Federal Circuit appeal preserved for reinstatement and the underlying district court case against Intel still live, this portfolio is actively enforced. The risk extends beyond Intel to any producer of logic cell array technology, configurable compute fabrics, or multi-processor bus architectures.
PatSnap Eureka’s FTO Search Agent allows R&D and IP teams to map their specific logic cell, bus system, or reconfigurable processor designs against the full PACT XPP portfolio in minutes. Eureka identifies claim overlaps, locates relevant prior art that may support design-around strategies, and surfaces related PACT filings that may not yet be asserted. For teams preparing for potential reinstatement of this Federal Circuit appeal, early FTO analysis is significantly cheaper than litigation defence.
Run a freedom-to-operate analysis on US8471593B2 to assess your product’s exposure
Run FTO in Eureka →Similar Federal Circuit appeals in reconfigurable processor and logic cell array patent disputes
Federal Circuit appeals involving reconfigurable processor, FPGA, and logic cell array patents against major semiconductor defendants — cases with comparable portfolio breadth and procedural posture.
What this case signals for the reconfigurable processor IP landscape
A dismissed-but-reinstateable appeal over 12 logic cell array patents keeps enforcement risk live for the entire semiconductor sector.
Premature appeals create reinstatement traps — monitor the 60-day clock
This case illustrates a procedural risk common in multi-claim patent suits: appealing before all district court claims are resolved strips the appellate court of jurisdiction. The conditional reinstatement mechanism here means the Federal Circuit appeal is paused, not ended. IP teams tracking PACT XPP litigation should watch for district court final judgment triggers that restart the appellate timeline.
PACT’s 12-patent portfolio signals sustained enforcement against processor makers
PACT XPP Schweiz is a focused IP assertion entity with a deep portfolio in reconfigurable logic and bus system architectures. Asserting 12 patents in a single infringement action against Intel suggests a broad claim coverage strategy. Companies in the FPGA, reconfigurable computing, and processor interconnect space should conduct proactive FTO analysis against PACT’s portfolio before district court proceedings conclude.
PACT v Intel — key questions answered
The appeal was dismissed because it was filed prematurely. Both parties jointly agreed the appeal was brought before a final judgment had been entered in the district court, specifically before pending counterclaims were resolved. The Federal Circuit requires a final judgment disposing of all claims before it has appellate jurisdiction. The dismissal was without prejudice to reinstatement.
Yes. The Federal Circuit’s order expressly permits reinstatement under the same docket number (25-1003) without payment of additional filing fees, provided PACT files a new notice of appeal within 60 days of entry of a final judgment in the underlying district court case. If the 60-day window expires, a new separately docketed appeal would be required.
PACT XPP asserted 12 US patents covering logic cell array and bus system technology: US8471593B2, US8312301B2, US8819505B2, US9436631B2, US9075605B2, US9552047B2, US9250908B2, US8686549B2, US9037807B2, US7928763B2, US8301872B2, and US9170812B2. All relate to reconfigurable processor architectures and programmable interconnect systems.
This standard provision in joint dismissal orders means neither party is awarded legal costs against the other arising from the appeal proceedings to date. It reflects the mutual agreement to dismiss and acknowledges that both sides shared responsibility for the premature filing situation. It carries no implication about the merits of the underlying infringement claims.
The dismissal is procedural and does not resolve infringement or validity of PACT’s 12-patent reconfigurable logic portfolio. The patents remain enforceable. Companies developing FPGA-adjacent, CGRA, or programmable bus interconnect technologies should note that this case is likely to resume at the Federal Circuit once district court proceedings conclude. Proactive FTO analysis against the PACT XPP portfolio is advisable for any company in the reconfigurable computing space.
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