pSemi Corp. vs. Cirrus Logic: Dismissed With Prejudice in Semiconductor Patent Dispute

📄 View Full Report 📥 Export PDF 🔗 Share ⭐ Save

Case Overview

In a case that underscores the high-stakes nature of semiconductor intellectual property disputes, pSemi Corp.’s patent infringement action against Cirrus Logic, Inc. concluded with a stipulated dismissal with prejudice on February 3, 2026—just 307 days after filing. Case No. 1:25-cv-00415, heard before Judge Gregory B. Williams in the United States District Court for the District of Delaware, involved three U.S. semiconductor patents and targeted Cirrus Logic’s LN8411 product line.

The outcome—a mutual dismissal with each party bearing its own attorneys’ fees and costs—offers no public admission of liability or wrongdoing by either side. Yet the resolution carries meaningful implications for semiconductor patent litigation strategy, freedom-to-operate (FTO) analysis, and the evolving dynamics between fabless semiconductor IP holders and integrated circuit developers. For patent attorneys, IP professionals, and R&D teams operating in the power management and analog semiconductor space, this case provides a valuable data point on assertion strategy, venue selection, and negotiated resolution timelines.

The Parties

⚖️ Plaintiff

A wholly owned subsidiary of Murata Manufacturing Co., Ltd., specializing in RF and power management integrated circuits with a robust patent portfolio.

🛡️ Defendant

A fabless semiconductor company known for high-precision analog and mixed-signal integrated circuits, serving audio, power conversion, and consumer electronics markets.

Patents at Issue

This litigation involved three recently issued U.S. patents in the semiconductor technology domain. Their high publication numbers indicate issuance within the 2024–2025 timeframe, reflecting pSemi’s active prosecution strategy in rapidly evolving semiconductor design areas.

  • US12212232B2 — Semiconductor architecture for power management ICs
  • US12143010B2 — High-efficiency power conversion methodologies
  • US12113438B2 — Integrated circuit design for analog and mixed-signal applications
🔍

Developing a new power management IC?

Check if your semiconductor design might infringe these or related patents before launch.

Run FTO Check →

The Verdict & Legal Analysis

Outcome

The case was resolved via stipulated dismissal with prejudice, jointly submitted by counsel from Quinn Emanuel and Morris Nichols. The order states: “All claims asserted in this case shall be dismissed with prejudice, with each party to bear its own attorneys’ fees, expenses, and costs.” No damages award, injunctive relief, or licensing terms were publicly disclosed. The “with prejudice” designation means pSemi cannot re-file the same claims against Cirrus Logic based on the same patents and same accused conduct.

Key Legal Issues

The case was initiated as a standard patent infringement action. Because the matter resolved by stipulation before trial or dispositive motion rulings, no judicial findings on infringement, validity, claim construction, or damages were issued. This means the case sets no binding legal precedent. The absence of a licensing disclosure, combined with each party bearing its own costs, suggests a confidential resolution, such as a cross-license, a design-around by Cirrus Logic, or a commercial negotiation.

Strategic Takeaways

This case reveals important insights into assertion strategy and resolution dynamics for recently issued semiconductor patents. The filing of suit based on patents issued within 12–18 months of the application’s progression through prosecution represents an increasingly common “fast-assertion” strategy, leveraging newly granted claims against concurrent competitive products.

For patent holders, asserting recently issued patents with claim mapping tied to specific competitor schematics demonstrates thorough pre-litigation preparation. For accused infringers, retaining experienced patent defense counsel early positions them favorably for both litigation and negotiation. The mutual cost-bearing structure suggests neither party achieved a clearly superior public outcome, reflecting balanced litigation posture.

⚠️

Freedom to Operate (FTO) Analysis

This case highlights critical IP risks in semiconductor design. Choose your next step:

📋 Understand This Case’s Impact

Learn about the specific risks and implications from this semiconductor litigation.

  • View all 80+ related patents in the power management IC space
  • See which companies are most active in semiconductor patents
  • Understand claim construction patterns in analog/mixed-signal ICs
📊 View Patent Landscape
⚠️
High Risk Area

Power management ICs & analog circuits

📋
80+ Related Patents

In power management IC space

Design-Around Options

Available for most claims

✅ Key Takeaways

For Patent Attorneys & Litigators

Stipulated dismissals with prejudice in Delaware semiconductor cases frequently reflect confidential licensing resolutions—monitor subsequent SEC filings.

Search related case law →

The absence of claim construction or invalidity rulings limits precedential value but preserves both parties’ IP positions for future assertions.

Explore precedents →
🔒
Unlock R&D Team Recommendations
Get actionable IP strategy steps for semiconductor product teams, including FTO timing guidance and design documentation best practices.
FTO against pending applications Rigorous design documentation Design-around strategies
Explore Full Analysis in PatSnap Eureka

Frequently Asked Questions

Ready to Strengthen Your Patent Strategy in Semiconductors?

Join 18,000+ IP professionals using PatSnap Eureka to conduct prior art searches, draft patents, and analyse competitive landscapes with AI-powered precision.

PatSnap IP Intelligence Team

Patent Research & Competitive Intelligence · PatSnap

This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.

The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.

📊 2B+ Patent Data Points 🌍 120+ Countries Covered 🏢 18,000+ Customers Worldwide ⚖️ Global Litigation Database 🔍 Primary Source Verified

References

  1. United States District Court for the District of Delaware — Case 1:25-cv-00415 (via PACER)
  2. U.S. Patent and Trademark Office — Patent Center
  3. PACER Case Locator
  4. Cornell Legal Information Institute
  5. PatSnap — IP Intelligence Solutions for Law Firms

This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.

⚖️ Disclaimer: This article is for informational purposes only and does not constitute legal advice. The analysis presented reflects publicly available case information and general legal principles. For specific advice regarding patent litigation, FTO analysis, or IP strategy, please consult a qualified patent attorney.