Rampart Asset Management, LLC v. NXP Semiconductors, N.V. et al.
Infringement action filed 13 Dec 2021 in the United States District Court for the Western District of Texas and closed 3 Oct 2023, with 7 patents asserted. Recorded basis of termination: dismissed with prejudice.
Case record
- Case no.
- 6:21-cv-01294
- Verdict cause
- Infringement action
- Court
- W.D. Tex.
- Court level
- District Court
- Case region
- Texas
- Chief judge
- Alan D Albright
- Trial level
- First instance
- Filed – Closed
- 13 Dec 2021 – 3 Oct 2023
- Duration
- 659 days
- Basis of termination
- Dismissed with Prejudice
- Products & marks
- DDR4 external memories · DDR4 memory controllers include pattern register circuitry · DDR4 memory controllers include a first circuit to transmit commands to the memory component · KLS1043 family · LS1017 family · LS1018 family · LS1020 family · LS1021 family · LS1022 family · LS1023 family · LS1026 family · LS1027 family · LS1028 family · LS1043 family · LS1046 family · LS1048 family · LS1084 family · LS1088 family · LS2044 family · LS2048 family · LS2084 family KS2088 family · LX2080 family · LX2082 family · LX2120 family · LX2122 family · LX2160 family · LX2162 family · MIMX8MD family · MIMX8ML family · MIMX8MM family · MIMX8MN family · MIMX8MQ family · Memory controllers that support one or more of the DDR3, DDR4,DDR, LPDDR3 and LPDDR4 standards · NXP KLS1023 family · PIMX8MQ family · The Multi-Purpose Register (MPR)
Check this patent against your own product
Prior art, claim scope, infringement exposure and design-around routes. Every answer cites the records behind it.
Get an FTO claim chart- 01Ranked prior artEvery hit source-linked
- 02Claim-level comparisonAgainst your own product
- 03Legal statusAcross 174 jurisdictions
Memory component with pattern register circuitry to provide data patterns for calibration
A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.
- Legal status
- Inactive
- Granted
- 1 Aug 2017
- Earliest priority
- 22 Oct 2001
- Est. expiry
- 22 Oct 2022
- Validity challenges
- None recorded
- Licences recorded
- None recorded
- Inventors
- HAMPEL, CRAIG E. · PEREGO, RICHARD E. · SIDIROPOULOS, STEFANOS · TSERN, ELY K. · WARE, FREDERICK A.
- Classification
- G11C11/4076G11C7/10G11C7/22G06F12/02G11C11/4078G11C11/4093G11C11/4072G06F3/06G11C21/00G11C11/406H04L7/00H10B43/27
- Prosecution counsel
- RAMBUS INC.
- Examiner
- PUENTE, EVA
Method and apparatus for coordinating memory operations among diversely-located memory components
A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
- Legal status
- Inactive
- Granted
- 6 Jan 2004
- Est. expiry
- 11 Feb 2022
- Validity challenges
- None recorded
- Licences recorded
- None recorded
- Inventors
- WARE, FREDERICK A. · TSERN, ELY K. · PEREGO, RICHARD E. · HAMPEL, CRAIG E.
- Classification
- G06F12/00G06F13/16G11C29/00G06F13/40G06F13/42G11C8/00G11C11/401G11C29/02
- Prosecution counsel
- RAMBUS INC.
- Examiner
- NGUYEN, T. V.
Also asserted in this case
5 moreThe docket lists 7 asserted patents. Full bibliographic detail, drawings and prosecution history for the remaining 5 asserted patents are one query away in Eureka.
- US8214616B2Memory controller device having timing offset capability
- US9367248B2Memory component with pattern register circuitry to provide data patterns for calibration
- US8472511B2Selectable-tap equalizer
- US7225311B2Method and apparatus for coordinating memory operations among diversely-located memory components
- US10192609B2Memory component with pattern register circuitry to provide data patterns for calibration
Parties of record
Rampart Asset Management, LLC
- Core tech
- G11C11/4076G11C7/10G11C7/22G06F12/02
- Counsel
- Joshua W. Rodriguez · Justine Minseon Park · Peter Lambrianakos · Raymond W. Mort III · Vincent J. Rubino III
- Firm
- Fabricant, LLP, The Mort Law Firm PLLC
NXP Semiconductors, N.V.
- Core tech
- Not recorded
- Counsel
- Barry K. Shelton · Bradley Dalton Coburn · Christopher Thomas Gresalfi · Steven N. Williams · William M. Logan · Winston Oliver Huff
- Firm
- Munsch, Hardt, Kopf & Harr PC, Winston Strawn LLP
- Also named
- NXP, B.V. · NXP Semiconductors USA, Inc. · NXP USA, Inc.
Counsel of record
Basis of termination
From the record · verbatim“The Court held a Markman hearing on September 30, 2022. During that hearing, the Court provided its final constructions. The Court now enters those claim constructions. SIGNED this 30th day of September, 2022.Text Order GRANTING98 Joint Motion to Dismissentered by Judge AlanDAlbright. (This isatext-only entry generated by thecourt. Thereis no documentassociated with thisentry.) (jslc) (Entered: 10/03/2023”
Case 6:21-cv-01294 · W.D. Tex. · closed 3 October 2023
Related cases
Three questions this record usually leads to. Each one runs against the full litigation and patent corpus, and cites what it finds.
Frequently asked questions
What is case 6:21-cv-01294?
6:21-cv-01294 is a patent infringement action brought by Rampart Asset Management, LLC against NXP Semiconductors, N.V., filed on 13 Dec 2021 in the United States District Court for the Western District of Texas. The case closed on 3 October 2023.
Which patents were asserted in 6:21-cv-01294?
US9721642B2 (“Memory component with pattern register circuitry to provide data patterns for calibration”), assigned to RAMPART ASSET MANAGEMENT, LLC, currently inactive; US6675272B2 (“Method and apparatus for coordinating memory operations among diversely-located memory components”), assigned to RAMPART ASSET MANAGEMENT, LLC, currently inactive; US8214616B2 (“Memory controller device having timing offset capability”), assigned to RAMPART ASSET MANAGEMENT, LLC; US9367248B2 (“Memory component with pattern register circuitry to provide data patterns for calibration”), assigned to RAMPART ASSET MANAGEMENT, LLC; US8472511B2 (“Selectable-tap equalizer”), assigned to RAMPART ASSET MANAGEMENT, LLC; US7225311B2 (“Method and apparatus for coordinating memory operations among diversely-located memory components”), assigned to RAMPART ASSET MANAGEMENT, LLC; US10192609B2 (“Memory component with pattern register circuitry to provide data patterns for calibration”), assigned to RAMPART ASSET MANAGEMENT, LLC. The record also lists DDR4 external memories, DDR4 memory controllers include pattern register circuitry, DDR4 memory controllers include a first circuit to transmit commands to the memory component, KLS1043 family, LS1017 family, LS1018 family, LS1020 family, LS1021 family, LS1022 family, LS1023 family, LS1026 family, LS1027 family, LS1028 family, LS1043 family, LS1046 family, LS1048 family, LS1084 family, LS1088 family, LS2044 family, LS2048 family, LS2084 family KS2088 family, LX2080 family, LX2082 family, LX2120 family, LX2122 family, LX2160 family, LX2162 family, MIMX8MD family, MIMX8ML family, MIMX8MM family, MIMX8MN family, MIMX8MQ family, Memory controllers that support one or more of the DDR3, DDR4,DDR, LPDDR3 and LPDDR4 standards, NXP KLS1023 family, PIMX8MQ family and The Multi-Purpose Register (MPR).
How was case 6:21-cv-01294 terminated?
The recorded basis of termination is dismissed with prejudice. The termination text reads: “The Court held a Markman hearing on September 30, 2022. During that hearing, the Court provided its final constructions. The Court now enters those claim constructions. SIGNED this 30th day of September, 2022.Text Order GRANTING98 Joint Motion to Dismissentered by Judge AlanDAlbright. (This isatext-only entry generated by thecourt. Thereis no documentassociated with thisentry.) (jslc) (Entered: 10/03/2023”
What does dismissal with prejudice mean?
A dismissal with prejudice permanently ends the claims that were filed, so the same claims cannot be brought again against that defendant. It is the usual form when the parties have settled.
How long did case 6:21-cv-01294 take?
659 calendar days, from filing on 13 Dec 2021 to closure on 3 October 2023.
Who were the attorneys and the judge in 6:21-cv-01294?
Chief Judge Alan D Albright presided. Joshua W. Rodriguez, Justine Minseon Park, Peter Lambrianakos, Raymond W. Mort III and Vincent J. Rubino III are recorded as counsel for plaintiff Rampart Asset Management. Barry K. Shelton, Bradley Dalton Coburn, Christopher Thomas Gresalfi, Steven N. Williams, William M. Logan and Winston Oliver Huff appear for defendant NXP Semiconductors, N.V..
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