Redstone Logics v. NXP Semiconductors: Semiconductor Patent Case Settled
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📋 Case Summary
| Case Name | Redstone Logics, LLC v. NXP Semiconductors, N.V. et al. |
| Case Number | 7:24-cv-00028 (W.D. Texas) |
| Court | Western District of Texas |
| Duration | Jan 2024 – May 2025 1 year 4 months |
| Outcome | Settled – Terms Undisclosed |
| Patents at Issue | |
| Accused Products | NXP’s i.MX 8 Family Application Processors |
Case Overview
The Parties
⚖️ Plaintiff
A patent assertion entity (PAE) whose IP portfolio targets semiconductor and processor technology, monetizing patent rights through licensing and, where necessary, litigation.
🛡️ Defendant
A global semiconductor leader with annual revenues exceeding $12 billion, specializing in automotive, industrial IoT, and embedded computing applications.
Patents at Issue
This case centered on U.S. Patent No. 8,549,339 B2, a processor-related patent asserting innovations relevant to power management, clock gating, or multi-core processing efficiency.
- • US 8,549,339 B2 — Processor architecture technology
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The Verdict & Legal Analysis
Outcome
The case concluded via joint stipulation of dismissal, reflecting a private resolution. Plaintiff’s claims were dismissed with prejudice, and defendant’s counterclaims dismissed without prejudice. Financial terms were not disclosed.
Key Legal Issues
The dismissal terms are strategically significant: Redstone Logics cannot re-litigate against NXP USA, Inc., but NXP preserves its right to pursue invalidity or other claims, potentially including inter partes review (IPR) at the USPTO’s PTAB.
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⚠️ Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor and processor design. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation in the semiconductor space.
- View all related patents in processor architecture
- See which companies are most active in semiconductor IP
- Understand claim construction patterns for processors
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High Risk Area
Processor power management & multi-core efficiency
Key Patent: US 8,549,339 B2
In processor architecture space
Design-Around Options
Available for most claims
✅ Key Takeaways
For Patent Attorneys & Litigators
Asymmetric dismissal terms (with/without prejudice) are a critical negotiating variable — always evaluate counterclaim preservation rights.
Search related case law →W.D. Texas remains a preferred venue for semiconductor NPE assertions; expect continued filing activity in this district.
Explore precedents →For R&D Leaders
Processor power management and multi-core resource allocation features carry elevated patent assertion risk; integrate FTO review into architectural design checkpoints.
Start FTO analysis for my product →Serial NPE campaigns targeting a product family can be anticipated — one settlement does not eliminate broader portfolio risk.
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