Rex Computing v. Cerebras Systems: Three AI Chip Patents, Dismissed With Prejudice After 4+ Years
Rex Computing filed suit against Cerebras Systems in Delaware, asserting three patents covering parallel processor and network-on-chip architecture against Cerebras’s Wafer Scale Engine, CS-1, and CS-2 deep learning systems. After 1,492 days of litigation, the parties jointly stipulated to dismissal with prejudice — each side absorbing its own legal costs — signalling a negotiated exit rather than a court-decided outcome.
Rival AI chip architectures collide — and quietly settle — in Delaware
On April 13, 2021, Rex Computing, Inc. filed suit against Cerebras Systems, Inc. in the District of Delaware before Judge Maryellen Noreika, asserting infringement of three US patents — US10700968B2, US10127043B2, and US10355975B2 — all originating from application filings in October 2016. The asserted patents cover foundational aspects of tiled processor architecture, inter-chip communication fabrics, and parallel compute design. Rex alleged that Cerebras’s commercially prominent products — including the Wafer Scale Engine, the CS-1 and CS-2 deep learning systems, the Graph Compiler, and the Swarm communication fabric — directly practised these inventions.
The case concluded on May 14, 2025, when the parties jointly filed a Rule 41(a)(1)(A)(ii) stipulation of dismissal with prejudice of all claims, defences, and counterclaims. Dismissal with prejudice is legally permanent: Rex cannot re-file these same patent claims against Cerebras on the same accused products. The mutual cost-bearing arrangement — each party paying its own attorneys’ fees — is consistent with a negotiated resolution, though no public settlement terms have been disclosed. The absence of a monetary judgment or injunction means the commercial outcome, if any, remains confidential.
The 1,492-day duration — over four years — suggests the case progressed through substantial pre-trial phases, likely including claim construction and fact discovery, before the parties reached their agreement. Cases of this length in Delaware typically reflect genuinely contested technical disputes rather than quick exits. What drove the final resolution is not apparent from the public record: it may reflect a licensing arrangement, a cross-licence, a payment, or simply a strategic reassessment of litigation risk by one or both parties. The three patents-in-suit remain in Rex’s portfolio and could, in principle, be asserted against different parties in the future.
Filing to Dismissed with Prejudice in 1492 days
1,492 days — well above the median D. Del. patent case resolution time of ~900 days
Dismissed with prejudice: what the joint stipulation means for both parties
Rule 41(a)(1)(A)(ii): a consensual, permanent exit
Under Federal Rule 41(a)(1)(A)(ii), parties may dismiss an action by filing a signed stipulation. Unlike a unilateral voluntary dismissal, this route requires both sides to agree — and the parties here chose dismissal with prejudice, meaning the court’s jurisdiction over these specific claims is permanently extinguished. No judicial merits ruling was ever issued on the patents-in-suit.
Bilateral stipulation — no merits rulingRex forfeits the right to re-sue Cerebras on these patents
Dismissal with prejudice operates as a final adjudication on the merits under res judicata principles. Rex Computing cannot re-assert US10700968B2, US10127043B2, or US10355975B2 against Cerebras on the same accused products. However, Rex’s patents remain enforceable against third parties. If Rex received value — licensing revenue, cross-licence rights, or a settlement payment — that information is not in the public record.
Patents survive; Cerebras claim barredCerebras secures permanent peace on these three patents
Cerebras obtains certainty: it cannot face suit from Rex on these three patents for the Wafer Scale Engine, CS-1, CS-2, Swarm fabric, or Graph Compiler again. Each side bearing its own costs also spares Cerebras from any fee-shifting exposure. Given Cerebras’s commercial trajectory in the AI accelerator market, achieving this resolution without a court-imposed injunction or damages award is commercially significant.
Permanent bar on Rex re-litigationTiled processor IP remains a live competitive battleground
The three Rex patents — covering parallel compute tile architecture and on-chip network fabrics — address technical territory directly relevant to modern large-scale AI chip design. Their survival in Rex’s portfolio means other wafer-scale or chiplet-based AI accelerator developers cannot treat this outcome as clearing the landscape. Companies designing competing architectures to Cerebras’s WSE should treat Rex’s portfolio as an ongoing FTO consideration.
Rex IP active against third partiesFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Rex Computing, Inc. | Company | Fabless semiconductor IP company — holder of US10700968B2, US10127043B2 & US10355975B2Search in Eureka ↗ |
| Defendant | Cerebras Systems, Inc. | Company | Cerebras Systems, Inc. — maker of the Wafer Scale Engine and CS-1/CS-2 AI accelerator systemsSearch in Eureka ↗ |
| Plaintiff counsel | Anthony David Raucci | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Brian P. Egan | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Mark Samartino | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Michael A. Berta | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Nicholas H. Lee | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Nicholas M. Nyemah | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Ryan J. Casamiquela | Attorney | Counsel for Rex Computing, Inc.Search in Eureka ↗ |
| Plaintiff law firm | Morris, Nichols, Arsht & Tunnell LLP | Law Firm | Representing Rex Computing, Inc.Search in Eureka ↗ |
| Defendant counsel | Dorronda R. Bordley | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Gavin Snyder | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | John S. Ferrell | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Kelly E. Farnan | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Kevin P.B. Johnson | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Robert J. Yorio | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Ron Hagiz | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Todd A. Noah | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Yury Kapgan | Attorney | Counsel for Cerebras Systems, Inc.Search in Eureka ↗ |
| Defendant law firm | Richards Layton & Finger PA | Law Firm | Representing Cerebras Systems, Inc.Search in Eureka ↗ |
| Presiding judge | Judge Maryellen Noreika | Judge | Delaware District CourtSearch in Eureka ↗ |
Official order — verbatim text
The stipulation is explicit and unambiguous: all claims, defences, and counterclaims are dismissed with prejudice, with each party bearing its own costs. The ‘with prejudice’ designation is legally critical — it forecloses any future Rex action against Cerebras on these three patents for the same accused products, functioning as a final merits bar under res judicata. The mutual cost-bearing clause removes any fee-shifting leverage and is typically a negotiated concession. Because dismissal was achieved by stipulation rather than judicial ruling, no claim construction, validity, or infringement findings appear in the public record — leaving the patents’ technical scope legally untested.
US10700968B2, US10127043B2 & US10355975B2 — Tiled Parallel Processor Architecture for AI
The three asserted patents — US10700968B2, US10127043B2, and US10355975B2 — share an October 2016 application priority date, placing them at the frontier of the modern AI accelerator hardware wave. They collectively cover foundational aspects of tiled processor design: how individual compute units are architecturally composed, how they communicate across an on-chip network fabric, and how memory and compute resources are distributed across a wafer-scale or multi-tile array. These technical domains are precisely the differentiating engineering decisions underlying Cerebras’s Wafer Scale Engine design philosophy.
For competitors active in AI accelerator hardware — including chiplet-based architectures, multi-die interconnect designs, and wafer-scale integration approaches — the Rex portfolio represents a non-trivial clearance challenge. The patents were filed before most commercial AI chip programmes reached production, giving them potential claim scope over architectures that were designed years later. The fact that Cerebras — a well-funded, technically sophisticated defendant — litigated for over four years rather than securing an early invalidity ruling suggests the patents have meaningful defensibility. Any company developing parallel AI processor hardware should treat these patents as high-priority FTO targets.
Should your team run an FTO against US10700968B2, US10127043B2 & US10355975B2?
If your organisation is designing, manufacturing, or commercialising AI accelerator hardware — particularly systems using tiled multi-core architectures, wafer-scale integration, or distributed on-chip communication fabrics — the Rex Computing portfolio demands formal freedom-to-operate analysis. The accused Cerebras products span the full stack: silicon (Wafer Scale Engine), systems (CS-1, CS-2), compiler software (Graph Compiler), and communication fabric (Swarm). That breadth of assertion signals Rex’s willingness to pursue both hardware and system-level infringement theories.
PatSnap Eureka’s FTO Search Agent can map your product’s compute tile topology, inter-core routing, and memory hierarchy against the claim language in US10700968B2, US10127043B2, and US10355975B2 in a fraction of the time traditional searches require. Eureka surfaces claim-by-claim prior art, identifies design-around opportunities, and flags related continuation or divisional applications that could extend Rex’s coverage. Given the 2016 priority dates, a thorough prosecution history review is also warranted to assess claim scope accurately.
Run a freedom-to-operate analysis on US10700968B2 to assess your product’s exposure
Run FTO in Eureka →Similar AI Chip and Parallel Processor Patent Cases in Delaware and the Federal Circuit
Cases below involve parallel processor, wafer-scale, or AI accelerator patent disputes litigated in Delaware District Court and related venues — the same technical and jurisdictional context as Rex v. Cerebras.
What this case signals for the AI accelerator and wafer-scale chip IP landscape
A four-year Delaware patent fight over AI chip architecture ending in mutual dismissal carries clear signals for IP strategy in the semiconductor AI sector.
Early-stage chip architecture patents carry real litigation teeth
Rex’s patents, filed in October 2016, predate the commercial AI accelerator boom. This case shows that foundational parallel-processing and on-chip network patents — even from smaller IP holders — can sustain four-plus years of contested litigation against well-capitalised defendants. Competitors designing tiled or wafer-scale processors should map relevant priority dates carefully.
Mutual cost-bearing dismissal typically signals a negotiated value transfer
When both parties absorb their own fees after years of expensive district court litigation, the economics rarely point to a pure walk-away. This structure is consistent with a confidential licensing or cross-licensing arrangement. IP professionals tracking Cerebras’s freedom to operate should assume some form of resolution was reached, even if undisclosed.
Rex v Cerebras — key questions answered
Rex Computing alleged that Cerebras Systems infringed three US patents — US10700968B2, US10127043B2, and US10355975B2 — covering tiled parallel processor architecture, on-chip network communication fabrics, and compute tile design. The accused products included the Cerebras Wafer Scale Engine, CS-1 and CS-2 deep learning systems, Graph Compiler, and Swarm communication fabric. The case was filed in Delaware in April 2021 and dismissed with prejudice in May 2025.
Dismissal with prejudice bars Rex from re-filing the same infringement claims against Cerebras on the same accused products — it functions as a final merits bar under res judicata. Critically, the three patents themselves remain in force and enforceable against other parties. Rex retains the right to assert US10700968B2, US10127043B2, and US10355975B2 against any other company whose products fall within the claims.
No settlement terms are disclosed in the public record. The parties filed a joint stipulation under Rule 41(a)(1)(A)(ii) agreeing to dismiss all claims with prejudice, with each side bearing its own costs and attorneys’ fees. The mutual cost-bearing structure and the four-year litigation duration are consistent with a confidential resolution involving undisclosed terms, but this remains speculative based on publicly available filings.
Rex accused the Cerebras Wafer Scale Engine (the core silicon), the CS-1 and CS-2 deep learning systems, the Cerebras Graph Compiler software, and the Swarm communication fabric. This broad product and software stack assertion suggests Rex pursued both hardware architecture and system-level infringement theories across the three asserted patents.
The patents — filed in October 2016 and covering tiled parallel processor architecture, inter-core network fabrics, and compute tile design — address technical principles applicable to a range of massively parallel processor architectures. While the case involved wafer-scale integration, the underlying claim language may have relevance to chiplet-based and multi-die interconnect designs depending on specific claim construction. Companies pursuing such architectures should conduct formal FTO analysis against this portfolio rather than assuming inapplicability.
PatSnap Eureka searches patents and litigation data to answer instantly.