Semiconductor Design Technologies v. Cadence Design Systems — Dismissed With Prejudice in 449 Days
Semiconductor Design Technologies, LLC asserted two EDA-related patents against Cadence Design Systems in the Northern District of California. The court granted Cadence’s motion to dismiss with prejudice, finding the asserted patents invalid on the pleadings and barring any refiling of the same claims.
Early patent-invalidity dismissal in the EDA software IP space
Semiconductor Design Technologies, LLC filed suit against Cadence Design Systems, Inc. on 6 March 2023 in the Northern District of California (Case No. 3:23-cv-01001), asserting infringement of two US patents: US7603636B2, directed to an assertion-generating system and method for circuit verification, and US7971167B2, covering a semiconductor design support device and associated manufacturing method. Cadence is one of the world’s leading providers of electronic design automation (EDA) software, making it a high-profile target for IP assertions in this sector.
The case closed on 28 May 2024 when Judge Rita F. Lin granted Cadence’s Motion to Dismiss with prejudice and without leave to amend the First Amended Complaint (FAC). The court concluded that no amendment could cure the validity defects in the asserted patents, citing the Federal Circuit’s Sanderling Management Ltd. v. Snap Inc. (65 F.4th 698, 2023) standard. Judgment was entered in favour of Cadence. A dismissal with prejudice on patent validity at the pleading stage is a decisive outcome — SDT is foreclosed from reasserting these patents against Cadence in federal court.
Resolution in 449 days without reaching claim construction or trial is consistent with Cadence mounting an aggressive Rule 12 strategy targeting patent eligibility or validity on the face of the pleadings. The Federal Circuit’s Sanderling citation suggests the court applied a § 101 or similar facial-invalidity analysis. What remains unknown from the public record is whether any licensing negotiations occurred prior to filing, the precise invalidity ground relied upon, and whether SDT holds related continuation patents that could form the basis of future actions against other EDA vendors.
Filing to settlement in 449 days
449 days — resolved before trial, well within median N.D. Cal. patent case duration
Motion to Dismiss granted with prejudice — patents held invalid on the pleadings
Dismissed on a Rule 12 motion — validity killed before discovery
Cadence secured dismissal at the pleading stage via a Motion to Dismiss, meaning the case ended before any substantive discovery, claim construction, or trial. Courts may dismiss patent infringement claims where the asserted patent is facially invalid — here, Judge Lin found the validity defects incurable. This is a resource-efficient and strategically powerful defence posture that denies the plaintiff any leverage from discovery costs.
Pre-discovery dismissalWith prejudice — SDT cannot refile these claims against Cadence
A dismissal with prejudice is a final adjudication on the merits. Unlike a without-prejudice dismissal, SDT cannot re-bring the same patent claims against Cadence in any federal court. The court’s explicit finding that ‘no amendment to the FAC would cure the validity problems’ closes off any attempt to salvage the action through amended pleadings. For Cadence, this provides durable legal certainty regarding these two specific patents.
Final — no refiling permittedSanderling v. Snap: the Federal Circuit standard applied
The court cited Sanderling Management Ltd. v. Snap Inc., 65 F.4th 698 (Fed. Cir. 2023), which confirmed that patent validity — particularly § 101 patent-eligibility — can be resolved on a motion to dismiss without claim construction where no factual disputes exist. This signals the invalidity determination here was reached on the face of the patents and FAC, without needing expert testimony or a Markman hearing.
§ 101 / facial invalidityTwo patents extinguished as enforcement tools against Cadence
While the judgment binds only SDT and Cadence, a with-prejudice dismissal grounded in patent invalidity sends a strong signal to other potential defendants. Any party currently accused under US7603636B2 or US7971167B2 — or anticipating such a claim — can reference this outcome in their own defence strategy. SDT’s ability to monetise these assets against the broader EDA industry is materially weakened by this ruling.
Weakened enforcement positionFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Semiconductor Design Technologies, LLC | Company | EDA-focused patent assertion entity — holder of US7603636B2 and US7971167B2Search in Eureka ↗ |
| Defendant | Cadence Design Systems, Inc. | Company | Cadence Design Systems, Inc. — global leader in electronic design automation (EDA) softwareSearch in Eureka ↗ |
| Plaintiff counsel | David L. Alberti | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Hong Lin | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | James P. Barabas | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Robert C. Mattson | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Robert F. Kramer | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Robert Y. Xie | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Russell Steven Tonkovich | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Plaintiff counsel | Sal Lim | Attorney | Counsel for Semiconductor Design Technologies, LLCSearch in Eureka ↗ |
| Defendant counsel | Christopher Scott Ponder | Attorney | Counsel for Cadence Design Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Ericka J Schulz | Attorney | Counsel for Cadence Design Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Harper Siems Batts | Attorney | Counsel for Cadence Design Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | James Young Hurt | Attorney | Counsel for Cadence Design Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Jeffrey Liang | Attorney | Counsel for Cadence Design Systems, Inc.Search in Eureka ↗ |
| Presiding judge | Judge Rita F. Lin | Chief Judge | California Northern District Court — Chief JudgeSearch in Eureka ↗ |
Stipulation of dismissal — official text
The court’s order is unambiguous in its finality: the motion to dismiss is granted with prejudice, no amendment is permitted, and judgment enters for Cadence. The explicit invocation of Sanderling v. Snap confirms the invalidity determination was made on facial review of the patents without claim construction — a high bar for plaintiffs to overcome on appeal. For SDT, the door is closed on these two patents against Cadence. For Cadence, this ruling provides clean clearance with no residual litigation risk from these specific assets.
US7603636B2 & US7971167B2 — EDA assertion generation and semiconductor design support
US7603636B2 (application no. US10/579766) covers an assertion-generating system, program, circuit verifying system, and associated method — tools used in formal or simulation-based hardware verification workflows. US7971167B2 (application no. US12/032117) is directed to a semiconductor design support device, design support method, and manufacturing method for semiconductor integrated circuits. Both patents address core stages of the IC design flow: verification and design methodology. The Sanderling citation in the dismissal order suggests the court found at least one of these patents to claim abstract or otherwise ineligible subject matter under 35 U.S.C. § 101.
In the EDA sector, assertion-based verification and design support automation are foundational capabilities embedded in commercial platforms. Cadence’s Jasper and Xcelium product lines, for instance, are widely used for formal verification and simulation. Any patent asserting broad coverage over assertion-generation or design-support workflows would, if valid, create significant exposure for EDA tool vendors and their customers. The court’s invalidity finding materially reduces the threat posed by these specific assets, but the broader technology space — hardware verification IP — remains actively contested by multiple patent holders.
Should your EDA or semiconductor design tool undergo FTO analysis against these patents?
Any company developing or deploying EDA tools that incorporate assertion-based verification, formal verification, or automated design support methods should assess their exposure to the patent families surrounding US7603636B2 and US7971167B2. While these patents were held invalid against Cadence, related continuation or divisional applications may still be live. Semiconductor IP teams at tool vendors, fabless chip companies, and EDA platform developers are all potential targets if related claims survive.
PatSnap Eureka’s FTO Search Agent can map the full patent family around application numbers US10/579766 and US12/032117, identify live related claims, and flag any claims that could read on your specific EDA workflows or chip design processes. Eureka’s claim-monitoring feature also alerts your team when continuation applications publish or when similar patents are asserted in litigation — keeping your FTO analysis current without manual docket monitoring.
Run a freedom-to-operate analysis on US7603636B2 to assess your product’s exposure
Run FTO in Eureka →Similar EDA and semiconductor design patent infringement cases in N.D. Cal.
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What this case signals for the EDA and semiconductor IP landscape
This dismissal demonstrates that patent validity in the EDA software domain remains acutely vulnerable at the pleading stage under current Federal Circuit doctrine.
EDA patent assertions face high facial-invalidity risk under § 101
Software-implemented EDA methods — including assertion generation and design support algorithms — sit squarely in the zone where courts apply rigorous § 101 scrutiny. Cadence’s success here suggests that EDA-focused patent holders must draft claims with concrete, machine-specific technical steps to survive a Rule 12 challenge. Generic process claims tied to semiconductor design workflows are increasingly vulnerable.
Rule 12 dismissal strategies are proving effective against NPE assertions in N.D. Cal.
Large technology defendants like Cadence consistently deploy pre-discovery dismissal motions to neutralise NPE actions before discovery costs create settlement pressure. N.D. Cal. judges, including Judge Lin, have demonstrated willingness to resolve patent validity at the pleading stage where the Federal Circuit has provided clear standards. Defendants in this district should evaluate Rule 12 motions as a first-line tool in EDA and software IP cases.
Semiconductor v Cadence — key questions answered
The case was dismissed with prejudice in favour of Cadence Design Systems. Judge Rita F. Lin granted Cadence’s Motion to Dismiss, finding the asserted patents (US7603636B2 and US7971167B2) invalid on the face of the pleadings and ruling that no amendment could cure the validity defects. Judgment was entered for Cadence on 28 May 2024.
The court found that the validity problems with the underlying patents were incurable — no amendment to the First Amended Complaint could fix them. The ruling cited Sanderling Management Ltd. v. Snap Inc., 65 F.4th 698 (Fed. Cir. 2023), suggesting the invalidity analysis was conducted on the face of the patents, consistent with § 101 abstract-idea or subject-matter eligibility grounds.
SDT asserted two patents: US7603636B2 (application US10/579766), covering an assertion-generating system, program, circuit verifying system, and assertion-generating method; and US7971167B2 (application US12/032117), directed to a semiconductor design support device, method, and manufacturing method for semiconductor integrated circuits. Both relate to EDA and IC design workflows.
Sanderling Management Ltd. v. Snap Inc., 65 F.4th 698 (Fed. Cir. 2023) confirmed that patent validity — particularly § 101 eligibility — can be resolved on a motion to dismiss without claim construction where the patent’s invalidity is apparent from the face of the complaint. Its citation here signals that the court applied that standard and found no factual dispute requiring further proceedings.
The judgment binds only the parties — SDT and Cadence. However, a with-prejudice invalidity dismissal citing a specific Federal Circuit standard weakens SDT’s enforcement position across the industry. Other EDA vendors or chip design companies targeted by these patents can reference this ruling in their own defence. Related continuation or divisional patents, if any, could still pose risk and warrant an independent FTO analysis.
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