Synopsys v. Avatar Integrated & Siemens: EDA Patent Dispute Dismissed With Prejudice
Synopsys, Inc. asserted three U.S. patents covering its IC Compiler and PrimeTime electronic design automation tools against Avatar Integrated Systems and Siemens Industry Software in California’s Northern District. After nearly four years of litigation, the parties jointly stipulated to dismiss the action with prejudice — each side bearing its own fees and costs.
Four-Year EDA Patent Battle Ends in Bilateral Dismissal
Synopsys, Inc. — a leading electronic design automation (EDA) software developer — filed suit on June 23, 2020 in the U.S. District Court for the Northern District of California against Avatar Integrated Systems, Inc. and Siemens Industry Software, Inc. Synopsys asserted three issued patents (US8407655B2, US7853915B2, and US8234614B1) covering technology embodied in its flagship IC Compiler and PrimeTime EDA tools, alleging infringement by the defendants.
On June 10, 2024 — 1,448 days after filing — the case ended via a Fed. R. Civ. P. 41(a)(1)(A)(ii) stipulated dismissal with prejudice. Critically, the parties agreed that each side bears its own attorneys’ fees and costs. A dismissal with prejudice is a final adjudication on the merits: Synopsys is permanently barred from reasserting these specific claims against these defendants. The bilateral cost-bearing arrangement suggests neither side extracted a clear financial concession from the other.
Nearly four years is a substantial investment for a case to resolve without a public merits determination, suggesting the parties likely reached a private commercial arrangement — though the public record is silent on any settlement terms. The involvement of Siemens Industry Software as a co-defendant alongside Avatar is strategically significant: Siemens is a direct EDA competitor to Synopsys, and its presence likely elevated the litigation’s complexity and stakes. What drove the ultimate resolution — licensing, cross-licensing, or simply a mutual decision to end hostilities — remains undisclosed.
Filing to Dismissed with Prejudice in 1448 days
1,448 days — nearly four years from filing to dismissal in N.D. Cal.
Dismissed with prejudice: what the stipulated exit means for both parties
Rule 41(a)(1)(A)(ii): stipulated dismissal with prejudice explained
A Fed. R. Civ. P. 41(a)(1)(A)(ii) dismissal is a joint stipulation signed by all parties — no court order required. The ‘with prejudice’ designation makes it a final adjudication: the same claims cannot be re-filed against the same defendants. This is the cleanest possible exit, giving defendants permanent protection from re-litigation of these specific patent claims.
Permanent bar on re-filingSynopsys permanently surrenders these claims against these defendants
By agreeing to dismissal with prejudice, Synopsys loses the right to reassert US8407655B2, US7853915B2, and US8234614B1 against Avatar and Siemens in future litigation. The patents themselves remain valid and enforceable against third parties. The bilateral cost arrangement means Synopsys recovers nothing publicly — any value exchanged, if any, would be in an undisclosed side agreement.
Claims extinguished vs. these defendantsAvatar and Siemens secured permanent immunity on these three patents
For Avatar Integrated Systems and Siemens Industry Software, the with-prejudice dismissal delivers full legal closure on the asserted claims. Neither defendant faces residual exposure from this action. The mutual cost-bearing term suggests defendants avoided any damages or royalty payment in the public record. Siemens — a market-level competitor to Synopsys — in particular benefits from removing litigation uncertainty.
Full closure, no public damagesEDA competitive dynamics: strategic settlement signals sector tension
The four-year duration and the involvement of Siemens Industry Software — a direct EDA rival to Synopsys — suggest this was more than a routine infringement suit. Cases involving IC Compiler and PrimeTime touch core EDA workflows. The quiet resolution is consistent with a cross-licensing or commercial arrangement that both sides preferred to keep confidential. EDA players should monitor whether Synopsys pursues related patents against other competitors.
EDA competitive IP tensionFull party and counsel information
| Role | Name | Type | Detail |
|---|---|---|---|
| Plaintiff | Synopsys, Inc. | Company | EDA software leader — holder of US8407655B2, US7853915B2, and US8234614B1Search in Eureka ↗ |
| Defendant | Avatar Integrated Systems, Inc. | Company | Avatar Integrated Systems, Inc. and Siemens Industry Software, Inc. — EDA sector defendantsSearch in Eureka ↗ |
| Co-Defendant | Siemens Industry Software, Inc. | Company | Search in Eureka ↗ |
| Plaintiff counsel | Aaron Stafford Oakley | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Alex Rhim | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Aliza George Carrano | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Barrington E. Dyer | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Brandon Keith Franklin | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Brian W Frino | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Celine Jimenez Crowson | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Corey T Leggett | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Gurtej Singh | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Helen Yiea Trac | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Jacob Karim | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | John Christopher Moulder | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Krista Sue Schwartz | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Madeleine Bech | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Nicholas Reddick | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Patrick Thomas Michael | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Shaimaa M Hussein | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff counsel | Xiaolin Chen | Attorney | Counsel for Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff law firm | Hogan Lovells US LLP (Washington DC) | Law Firm | Representing Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff law firm | Hogan Lovells US LLP | Law Firm | Representing Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff law firm | Seyfarth Shaw LLP | Law Firm | Representing Synopsys, Inc.Search in Eureka ↗ |
| Plaintiff law firm | Willkie Farr Gallagher LLP | Law Firm | Representing Synopsys, Inc.Search in Eureka ↗ |
| Defendant counsel | Caroline L Desmond | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | John D. Vandenberg | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Jonah Dylan Mitchell | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Klaus Hemingway Hamm | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Kristin L. Cleveland | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Mark W. Wilson | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Paul Alexander | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Salumeh R Loesch | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant counsel | Scott D. Baker | Attorney | Counsel for Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant law firm | Arnold & Porter Kaye Scholer LLP | Law Firm | Representing Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant law firm | Klarquist, Sparkman LLP | Law Firm | Representing Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Defendant law firm | Reed Smith LLP | Law Firm | Representing Avatar Integrated Systems, Inc.Search in Eureka ↗ |
| Presiding judge | Judge N/A | Judge | California Northern District CourtSearch in Eureka ↗ |
Official order — verbatim text
The stipulated dismissal under Rule 41(a)(1)(A)(ii) reflects a consensual, bilateral exit rather than any merits adjudication. The ‘with prejudice’ language is the operative term: it functions as a final judgment barring Synopsys from re-litigating these three patent claims against Avatar and Siemens in any future proceeding. The mutual cost-bearing clause is notable — it departs from any fee-shifting outcome and suggests both parties valued finality over a contested cost determination. No finding of invalidity, non-infringement, or infringement was ever entered on the public record.
US8407655B2, US7853915B2 & US8234614B1 — EDA Tool Patents
The three patents at issue — US8407655B2, US7853915B2, and US8234614B1 — cover technology in the electronic design automation domain, specifically methods and systems underlying Synopsys’s IC Compiler (place-and-route) and PrimeTime (static timing analysis) product lines. These are among Synopsys’s most commercially critical tools, used at foundries and fabless semiconductor companies globally to physically implement and verify chip designs. The application dates (application numbers 12/949689, 12/145405, and 12/156963) suggest late-2000s to early-2010s vintage filings, meaning these patents would have issued with claims shaped around EDA methodologies that were maturing as advanced node design complexity surged.
Strategically, patents covering core EDA workflow steps — compilation, timing closure, and layout optimization — create a high barrier for competitors seeking to replicate equivalent functionality. Synopsys’s decision to assert all three patents simultaneously against Avatar and Siemens suggests a coordinated enforcement posture designed to protect market share in a segment where Siemens (via its EDA acquisitions) has aggressively expanded. Any EDA software vendor, ECAD tool developer, or semiconductor IP provider building tools that intersect with IC place-and-route or static timing verification should treat this patent family as a live clearance priority.
Should you run an FTO against US8407655B2, US7853915B2 & US8234614B1?
If your R&D team is building or acquiring EDA tools that touch IC place-and-route compilation or static timing analysis — the core workflows of IC Compiler and PrimeTime — these three Synopsys patents represent a meaningful clearance priority. The with-prejudice dismissal only protects Avatar and Siemens from re-assertion; all other market participants remain fully exposed. Chip design tool vendors, EDA startups, and semiconductor OEMs integrating third-party design automation capabilities should assess whether their implementations overlap with the claim scope of these patents before product launch or licensing negotiations.
PatSnap Eureka’s FTO Search Agent can map the independent and dependent claim structures of US8407655B2, US7853915B2, and US8234614B1 against your technical implementation, surfacing design-around opportunities and prosecution history estoppel that may limit claim scope. Eureka also identifies continuation applications and related family members that Synopsys may assert separately — giving your legal and engineering teams a complete exposure picture before entering the EDA competitive market.
Run a freedom-to-operate analysis on US8407655B2 to assess your product’s exposure
Run FTO in Eureka →Similar EDA Patent Infringement Cases in N.D. California
Cases involving EDA software patents litigated in the Northern District of California, including Synopsys enforcement actions and electronic design automation IP disputes.
Related patent case — similar technology
Comparable case in the same technology domain. Patent holder and defendant reached resolution after proceedings.
SettledRelated infringement action — same court
Comparable IC Compiler-adjacent infringement action. Patent enforcement dynamics analysed in depth.
Active · District CourtRelated invalidity challenge — appellate outcome
Combined invalidity and infringement action in the same technology space. Decided after substantive proceedings.
DecidedSynopsys, Inc.’s broader IP enforcement history
Synopsys, Inc.’s full litigation history covering prior enforcement, licensing activity, and inter partes review proceedings.
Portfolio viewWhat this case signals for the EDA software IP landscape
A four-year, three-patent EDA dispute between direct competitors ending in bilateral dismissal carries clear market signals for IP strategy teams.
EDA patents covering core workflow tools carry significant litigation leverage
Synopsys’s choice to assert three patents specifically tied to IC Compiler and PrimeTime — its most commercially central tools — signals that EDA incumbents are willing to use their deep patent portfolios to challenge competitive encroachment. Any EDA platform replicating comparable chip compilation or timing analysis functionality faces meaningful patent risk from this portfolio.
Dismissal with prejudice plus mutual cost-bearing often signals a private resolution
When sophisticated parties walk away from four years of litigation with no public damages and a with-prejudice stipulation, the pattern is consistent with an undisclosed commercial arrangement — licensing, cross-licensing, or a business relationship restructuring. The public record cannot confirm this, but the structure is a common signal in high-value EDA and enterprise software disputes.
Synopsys’s three asserted patents remain live weapons against other EDA players
The with-prejudice dismissal only extinguishes claims against Avatar and Siemens. US8407655B2, US7853915B2, and US8234614B1 remain valid and enforceable. Any EDA competitor, integrator, or OEM building tools that touch IC place-and-route or static timing analysis should assess exposure to this patent family before product launch or expansion.
Siemens’s co-defendant status reflects deepening EDA consolidation IP risk
Siemens’s presence as a co-defendant alongside a smaller player like Avatar suggests Synopsys may have been targeting the larger acquirer’s broader product integration. As EDA consolidates further, IP portfolios protecting core workflow software will become increasingly contested — acquirers of EDA assets should treat patent clearance on IC design tools as a pre-close requirement.
Synopsys v Avatar — key questions answered
The case was dismissed with prejudice on June 10, 2024, via a stipulated dismissal under Fed. R. Civ. P. 41(a)(1)(A)(ii). Each party agreed to bear its own fees and costs. No merits determination — such as a finding of infringement or invalidity — was entered on the public record.
Synopsys asserted three U.S. patents: US8407655B2 (App. No. 12/949689), US7853915B2 (App. No. 12/145405), and US8234614B1 (App. No. 12/156963). All three relate to EDA technology underlying the IC Compiler and PrimeTime product lines covering chip place-and-route and static timing analysis workflows.
A with-prejudice dismissal permanently bars Synopsys from re-filing the same claims against Avatar Integrated Systems and Siemens Industry Software. The patents remain valid and enforceable against other parties. Synopsys can still assert US8407655B2, US7853915B2, and US8234614B1 against any third party not covered by the stipulation.
The case data does not specify the precise role distinction, but Siemens Industry Software is a direct EDA competitor to Synopsys following its acquisitions in the EDA space. Its co-defendant status alongside Avatar suggests Synopsys may have been targeting product integration or distribution relationships between the two entities that allegedly involved the asserted patents.
The case ran for 1,448 days — approximately four years — from filing on June 23, 2020 to dismissal on June 10, 2024. This duration is consistent with complex multi-defendant patent litigation in the Northern District of California, where EDA and enterprise software cases often involve extensive claim construction and technical expert discovery before resolution.
Track EDA Patent Enforcement Risk Before It Reaches Litigation
Run an FTO on the Synopsys EDA patent family before building or acquiring IC Compiler or PrimeTime-adjacent technology. PatSnap Eureka monitors live enforcement activity across the EDA software patent landscape so your IP team stays ahead of risk.
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