VLSI Technology v. Intel: Semiconductor Patent Dispute Ends in Split Verdict
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📋 Case Summary
| Case Name | VLSI Technology, LLC v. Intel Corporation |
| Case Number | 5:17-cv-05671 (N.D. Cal.) |
| Court | U.S. District Court for the Northern District of California |
| Duration | Oct 2017 – Mar 2024 6 years 5 months |
| Outcome | Split Verdict — No Damages Reported |
| Patents at Issue | |
| Accused Products | Intel Atom, Core i3/i5/i7, Xeon processors, EMIB, Stratix 10 FPGAs, Turbo Boost Max Technology 3.0 |
After 2,370 days of contentious litigation, the U.S. District Court for the Northern District of California entered a landmark split judgment in *VLSI Technology, LLC v. Intel Corporation* (Case No. 5:17-cv-05671), closing one of the most complex semiconductor patent disputes in recent memory. Filed on October 2, 2017, and resolved on March 29, 2024, the case pitted patent assertion entity VLSI Technology against semiconductor giant Intel across eight asserted patents covering critical microprocessor technologies — from power management to memory architecture.
The court’s judgment delivered mixed results: Intel prevailed on VLSI’s infringement claims for U.S. Patent Nos. 8,004,922 and 8,566,836, while VLSI successfully defeated Intel’s counterclaim seeking a declaratory judgment of license. For patent litigators, IP professionals, and R&D teams operating in the semiconductor space, this case offers critical lessons in multi-patent assertion strategy, summary judgment practice, and the limits of license-based counterclaims in patent infringement litigation.
Case Overview
The Parties
⚖️ Plaintiff
Patent assertion entity that acquired a portfolio of semiconductor-related patents originally developed at NXP Semiconductors and its predecessors.
🛡️ Defendant
World’s largest semiconductor manufacturer by revenue, producing accused microprocessor product lines.
The Patents at Issue
This landmark case involved eight patents covering critical microprocessor technologies across a wide range of semiconductor innovations:
- • U.S. Patent No. 7,706,207 — Memory/data path architecture
- • U.S. Patent No. 8,004,922 — Semiconductor timing and signal integrity
- • U.S. Patent No. 8,020,014 — Power management systems
- • U.S. Patent No. 7,268,588 — Circuit design and integration
- • U.S. Patent No. 7,675,806 — On-chip interconnect technology
- • U.S. Patent No. 7,709,303 — Semiconductor fabrication processes
- • U.S. Patent No. 8,268,672 — Chip packaging and integration
- • U.S. Patent No. 8,566,836 — Memory interface architecture
The Accused Products
VLSI accused a broad range of Intel products, including Atom microprocessors, Core i3/i5/i7 processors, Xeon E3/E5/E7 server processors, Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, Stratix 10 FPGAs, and Turbo Boost Max Technology 3.0 — underscoring the sweeping commercial scope of VLSI’s infringement allegations.
Legal Representation
VLSI retained a formidable plaintiff-side team led by Irell & Manella LLP, Kirkland & Ellis LLP, Bunsow DeMory LLP, and Dickinson Wright PLLC, with prominent attorneys including Morgan Chu and Benjamin Hattenbach. Intel was represented by WilmerHale LLP, Gibson, Dunn & Crutcher LLP, and K&L Gates LLP, fielding counsel including William F. Lee and Joseph J. Mueller.
Litigation Timeline & Procedural History
VLSI filed suit in the Northern District of California — a technically sophisticated venue well-suited to complex semiconductor patent disputes — on October 2, 2017. The case proceeded at first-instance (district court) level through nearly six and a half years of litigation before final judgment on March 29, 2024.
Key procedural milestones included extensive cross-motions for summary judgment, which proved dispositive on multiple patent counts. The court’s order granting in part and denying in part the parties’ summary judgment motions (ECF Nos. 772 & 778) resolved the infringement questions on U.S. Patent Nos. 8,004,922 and 8,566,836 in Intel’s favor. A separate motion to dismiss Intel’s license counterclaim (ECF No. 903) was granted in VLSI’s favor. Remaining claims were resolved through party stipulations and mootness findings (ECF Nos. 801 & 807).
The case’s 2,370-day duration reflects the complexity inherent in multi-patent semiconductor litigation involving dozens of accused products, extensive claim construction proceedings, and high-stakes summary judgment practice on both validity and infringement grounds.
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The Verdict & Legal Analysis
Outcome
The Northern District of California entered a split final judgment resolving all counts in this action:
Intel prevailed on:
- • VLSI’s Fifth Count — Infringement of U.S. Patent No. 8,004,922
- • VLSI’s Eighth Count — Infringement of U.S. Patent No. 8,566,836
- • Intel’s Tenth Counterclaim — Invalidity of U.S. Patent No. 8,004,922
VLSI prevailed on:
- • Intel’s Seventeenth Counterclaim for Declaratory Judgment of License — dismissed without prejudice to refiling in a proper forum
All remaining claims and counterclaims were dismissed. No damages award or injunctive relief was reported in the final judgment.
Verdict Cause Analysis
The resolution of the two pivotal infringement counts — U.S. Patent Nos. 8,004,922 and 8,566,836 — at the summary judgment stage rather than at trial is strategically significant. Summary judgment victories for defendants in patent cases typically require either clear non-infringement as a matter of law following claim construction, or successful invalidity showings on undisputed facts. Here, Intel secured a finding of invalidity on the ‘922 patent alongside non-infringement, a dual outcome that eliminated any appellate risk of the patent surviving on remand.
VLSI’s defeat on its license counterclaim defense — specifically, the court’s dismissal of Intel’s declaratory judgment claim regarding a license to VLSI’s patents — signals the court’s determination that Intel had not established licensing entitlements in this forum. The “without prejudice” qualifier preserves Intel’s ability to pursue that argument elsewhere, suggesting the dismissal was jurisdictional or procedural rather than substantive.
Legal Significance
Several doctrinal considerations emerge from this outcome. First, the invalidity finding on U.S. Patent No. 8,004,922 carries potential collateral estoppel weight in any parallel or subsequent proceedings involving that patent. Patent assertion entities relying on the same portfolio in multi-district litigation strategies must account for this risk. Second, the dismissal of a license-based declaratory judgment counterclaim reinforces the importance of establishing proper forum and factual predicates for such defensive claims before asserting them in infringement litigation.
The case also illustrates the viability of summary judgment as a trial-avoidance strategy in technically complex semiconductor patent cases, particularly when defendants can mount strong claim construction and invalidity arguments.
Strategic Takeaways
For patent holders: Multi-patent assertion strategies spread litigation risk but also create compounded vulnerability at summary judgment. VLSI’s experience underscores the importance of curating asserted claims to ensure each patent can withstand rigorous invalidity scrutiny before litigation.
For accused infringers: Intel’s success on summary judgment demonstrates that investing in early invalidity analysis and parallel USPTO proceedings (IPR/PGR) creates viable pathways to case resolution without trial exposure. License counterclaims require careful jurisdictional and contractual analysis before assertion.
For R&D teams: Products accused here — Core, Xeon, Atom, and EMIB technologies — represent Intel’s entire commercial microprocessor ecosystem. This broad accusation pattern highlights the freedom-to-operate (FTO) risks that inherited patent portfolios from legacy semiconductor companies (NXP, Philips lineage) continue to pose to chip manufacturers.
Industry & Competitive Implications
VLSI v. Intel is part of a broader wave of semiconductor patent assertions by NPEs holding portfolios acquired from divested legacy chip businesses. The case reflects an industry-wide licensing pressure dynamic in which major foundries and fabless manufacturers face multi-front litigation from entities monetizing decades-old semiconductor IP.
Intel’s ultimate success on the two most hotly contested patents — combined with the lengthy litigation timeline — sends a clear message: well-resourced defendants can effectively neutralize NPE assertions through persistent invalidity and claim construction challenges, even at significant cost and duration. For Intel, the resolution avoids any damages exposure on these specific patents while preserving its commercial product roadmap.
For the broader semiconductor industry, this outcome reinforces the value of proactive IPR petitions at the Patent Trial and Appeal Board as a companion strategy to district court litigation. Companies facing similarly broad NPE assertions in the Northern District of California should monitor this case’s claim construction orders as persuasive authority in related proceedings.
Licensing practitioners should note that VLSI’s parallel litigations against Intel in other jurisdictions — including *VLSI Technology v. Intel* in the Western District of Texas — produced different outcomes, illustrating the significant impact of venue selection on semiconductor patent litigation results.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in semiconductor design. Choose your next step:
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High Risk Area
Semiconductor timing and memory architectures
8 Asserted Patents
In semiconductor IP space
Summary Judgment Wins
Demonstrates defense viability
✅ Key Takeaways
Summary judgment remains a powerful tool in semiconductor patent litigation when supported by strong invalidity evidence and precise claim construction arguments.
Search related case law →Invalidity findings carry collateral estoppel risk across parallel NPE litigations — assess portfolio-wide exposure when defending multi-patent assertions.
Explore precedents →License-based declaratory judgment counterclaims require clear jurisdictional and contractual foundations before assertion.
View legal strategy guides →Northern District of California continues to be a technically sophisticated venue for complex semiconductor IP disputes.
Analyze venue statistics →Patent assertion entities leveraging legacy semiconductor portfolios (NXP, Philips lineage) remain an ongoing licensing risk for major chip manufacturers.
Track NPE activity →Multi-venue NPE litigation strategies produce variable outcomes — portfolio managers should track claim construction rulings across all active forums.
Monitor claim construction trends →Intel’s full commercial product ecosystem — including EMIB packaging and Turbo Boost technologies — demonstrates that virtually no modern processor architecture is immune from legacy patent assertions.
Start FTO analysis for my product →Proactive FTO analysis on acquired or inherited semiconductor IP portfolios is essential risk management, particularly for next-generation chip architectures.
Try AI patent drafting →Companies should continuously monitor patent landscapes related to their core technologies, especially when engaging in M&A involving IP portfolios.
Explore competitive intelligence →Frequently Asked Questions
Eight U.S. patents were asserted, covering semiconductor timing, power management, memory interface, chip packaging, and on-chip interconnect technologies, including U.S. Patent Nos. 7,706,207; 8,004,922; 8,020,014; 7,268,588; 7,675,806; 7,709,303; 8,268,672; and 8,566,836.
The court granted summary judgment of non-infringement on both patents and additionally found U.S. Patent No. 8,004,922 invalid, resolving those claims before trial based on undisputed facts and claim construction determinations.
The split outcome reinforces the effectiveness of summary judgment as a trial-avoidance mechanism and highlights the strategic importance of invalidity challenges in defending against NPE assertions covering broad commercial microprocessor product lines.
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PatSnap IP Intelligence Team
Patent Research & Competitive Intelligence · PatSnap
This analysis was produced by the PatSnap IP Intelligence Team — a group of patent analysts, IP strategists, and data scientists who work daily with PatSnap’s global patent database of over 2 billion structured data points across patents, litigation records, scientific literature, and regulatory filings.
The team specialises in tracking landmark litigation outcomes, translating complex court rulings into actionable IP strategy, and identifying the competitive intelligence implications for R&D and legal teams. All case analysis is grounded in primary sources: official court records, USPTO filings, and Federal Circuit opinions.
References
- PACER Case Filing 5:17-cv-05671
- USPTO Patent Full-Text Database
- PTAB IPR Proceedings Search
- PatSnap — IP Intelligence Solutions for Law Firms
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.
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