Western Digital v. Viasat: Flash Memory Patent Dispute Ends in Voluntary Dismissal
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📋 Case Summary
| Case Name | Western Digital Corp. v. Viasat, Inc. |
| Case Number | 24-1393 (Fed. Cir.) |
| Court | Federal Circuit |
| Duration | Jan 26, 2024 – Apr 24, 2024 89 days |
| Outcome | Voluntary Dismissal – No Damages |
| Patents at Issue | |
| Accused Products | Error correction architecture embedded within flash memory systems |
Case Overview
The Parties
⚖️ Plaintiff-Appellant
Global leader in data storage solutions, holding an extensive IP portfolio spanning flash memory architecture, NAND storage, and error correction technologies.
🛡️ Defendant
Known for satellite communications, also maintains IP interests in data transmission and error correction technologies relevant to flash memory error management systems.
The Patent at Issue
This case involved U.S. Patent No. 8,615,700 B2, covering forward error correction (FEC) with parallel error detection for flash memories, a technology foundational to high-reliability data storage systems.
- • US 8,615,700 B2 — Forward error correction (FEC) with parallel error detection for flash memories
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The Verdict & Legal Analysis
Outcome
The Federal Circuit issued an order of voluntary dismissal under **Fed. R. App. P. 42(b)** upon the parties’ joint agreement. No damages were awarded, and no injunctive relief was granted or denied. The dismissal was purely procedural, with each side bearing its own costs, leaving no published merits ruling on claim validity, claim construction, or infringement.
Key Legal Issues
The case was classified as an invalidity/cancellation action, suggesting the appeal likely arose from a Patent Trial and Appeal Board (PTAB) proceeding or a district court invalidity determination. Because the parties dismissed before any Federal Circuit opinion was issued, no claim construction ruling, validity determination, or infringement finding entered the public record. The patent’s legal status and enforceability post-dismissal would depend entirely on outcomes from the proceeding below, which are not specified in available case data.
Freedom to Operate (FTO) Analysis
This case highlights critical IP risks in flash memory design and error correction. Choose your next step:
📋 Understand This Case’s Impact
Learn about the specific risks and implications from this litigation in flash memory.
- View all related patents in this technology space
- See which companies are most active in flash memory IP
- Understand error correction claim construction patterns
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High Risk Area
Forward error correction (FEC) in flash memory
Related Patents
In flash memory and error correction
Design-Around Options
Available for many FEC implementations
✅ Key Takeaways
Voluntary Federal Circuit dismissals under Rule 42(b) leave lower-level validity determinations intact — understand what record survives.
Search related case law →Mutual cost-bearing suggests negotiated resolution; investigate related licensing activity.
Explore precedents →Frequently Asked Questions
The case concerned U.S. Patent No. 8,615,700 B2 (Application No. 12/858,510), covering forward error correction with parallel error detection for flash memories.
The parties agreed to voluntary dismissal under Fed. R. App. P. 42(b), with each side bearing its own costs. No merits ruling was issued by the Federal Circuit.
The unresolved appellate status of U.S. 8,615,700 B2 leaves its validity and enforceability dependent on lower-level proceedings. Companies in the flash memory and error correction space should monitor this patent family closely.
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References
- United States Court of Appeals for the Federal Circuit — Case 24-1393
- USPTO Patent Center – U.S. 8,615,700 B2
- PACER Case Locator – Case No. 24-1393
- PatSnap — IP Intelligence Solutions for Semiconductors
This article is for informational purposes only and does not constitute legal advice. All case information is drawn from publicly available court records. For platform capabilities, visit PatSnap.