2.5D Interposer Patents: Who Leads, Where the Gaps Are 2026
- Filing has flattened, not grown. activity peaked at 13 families in 2023 after a 2022 trough of just 2, a pattern more consistent with a maturing claim base than an expanding one.
- The most-cited prior art is a decade old. the highest-cited record in this set dates to 2015-era publication (US20170084596A1, 116 citations), meaning current design-around work has to route through art that predates most active competitors' portfolios.
- Filing is US-centric with a thin PCT layer. 67 of the tracked records came through the USPTO versus 8 via WIPO, a filing pattern that concentrates enforcement risk in one jurisdiction rather than spreading it globally.
What this landscape covers
This review tracks patent families claiming silicon interposer, 2.5D packaging and embedded silicon bridge structures, filtered to filings that also address through silicon via formation, fine pitch microbump interconnect, warpage control, HBM integration or assembly yield. The scope sits at the intersection of three IPC classes covering semiconductor devices and their manufacture, which keeps the set focused on interposer-level integration rather than general packaging or die-level circuit design.
The 109 families span filings from 2015 through the 2026 data cut-off. Because publication typically lags filing by around 18 months, the most recent one to two years in any trend line will always look thinner than the underlying filing activity actually was.
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Filing trend and technology composition
Two views of the same 109-family set: how filing volume has moved year over year, and how those families distribute across the IPC subclasses that make up the interposer and bridge packaging space.
A flat-to-declining filing curve
Filings opened at 12 in 2017, dropped to a 2022 midpoint of just 2, then recovered to a peak of 13 in 2023. That shape reads as a technology whose core claims were staked out early, went quiet, then saw a renewed but not sustained push – not a market in steady expansion.
Concentration in core semiconductor device classes
All 109 records sit in H01L, and just over half (54) additionally touch H10W. Secondary classes – H10D, H10P, H10B, B81B, G06N and H05K – each cover under 10 records, indicating the bulk of claim activity is packaged around core device and via structures rather than adjacent memory manufacture, MEMS or AI-specific compute integration.
Shares are the percentage of the 109 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on 2.5D Interposer and Silicon Bridge Packaging with Eureka
This page is one run against one query. Ask Eureka your own question about 2.5d interposer and silicon bridge packaging and every answer comes back with the patent numbers behind it.
Try EurekaThe prior art carrying the most citation weight
Integrated circuit packaging system with stackable package and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side.Filed by STATS ChipPac Management, published 2011-06-02 – one of the earlier records in this set to tie a through silicon via interposer directly to a stackable, encapsulated package architecture.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20170084596A1 | Thermally enhanced fully molded fan-out module | 116 |
| 2 | US20120261805A1 | Through package via structures in panel-based silicon substrates and methods of making the same | 57 |
| 3 | US20130210198A1 | Process for forming semiconductor structure | 56 |
| 4 | US20140001639A1 | Semiconductor device having silicon interposer on which semiconductor chip is mounted | 54 |
| 5 | US11694940B1 | 3D stack of accelerator die and multi-core processor die | 51 |
| 6 | US20210074645A1 | Chip package structure using silicon interposer as interconnection bridge | 44 |
| 7 | US20100244223A1 | Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof | 44 |
| 8 | US20190164806A1 | Non-embedded silicon bridge chip for multi-chip module | 35 |
| 9 | US20210375768A1 | Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of fo… | 32 |
| 10 | US20100155888A1 | Silicon interposer testing for three dimensional chip stack | 31 |
Citation counts are drawn from the searched corpus only and favour older filings by construction; treat them as a measure of influence on later filers, not of present-day commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers say about the state of the field
Four read-outs from the filing trend, citation table and jurisdiction split that matter for a freedom-to-operate or whitespace decision.
Growth has not been sustained since the 2023 peak
The 2026 figure is partial by design given publication lag, but the run-up from a 2022 low of 2 to a 2023 high of 13 and back down again suggests bursts of filing tied to specific product cycles rather than a steadily compounding technology area.
Enforcement exposure concentrates in the United States
With South Korea (11), China (15) and Taiwan (4) trailing the US total and PCT filings thin at 8, most applicants appear to be protecting US commercial exposure first and treating multi-jurisdiction coverage as secondary.
The most influential prior art predates the recent filing wave
The highest-cited record in the set, on thermally enhanced fan-out molding, and the next several most-cited records on TSV and interposer-mounting structures were all published years before the 2023 filing peak – later filers are building on, not replacing, this base.
Collaboration between assignees is rare in this corpus
Only two co-assignee pairs appear across 109 families, both involving IBM entities in different jurisdictions, indicating most interposer and bridge packaging IP here is developed and held by single corporate applicants rather than joint ventures.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to 2.5d interposer and silicon bridge packaging, with the prior art for and against each one.
Who holds the ground, and where momentum has stalled
Recent-year momentum data shows a distinctive pattern: the named assignees with the largest historical presence in this corpus all show zero filings in the latest tracked year, several down from positive prior-year activity.
Historical leaders have gone quiet in the most recent window
Assignees including Siliconware Precision Industries, IBM, Chipbond Technology, TSMC, Kepler Computing and ASE Technology each show zero filings in the latest tracked year, with Siliconware showing a -100% year-over-year drop. Given publication lag, some of this is measurement artefact rather than an actual pullback, but the consistency across six separate large filers is notable.
A moderately sized, single-technology corpus
At 109 families this is a focused rather than sprawling landscape – large enough to show real concentration patterns among named assignees, small enough that a handful of additional filings from any one player would visibly shift the ranking.
Entry gates cluster around three examination regimes
A new entrant's freedom-to-operate exposure is concentrated almost entirely in US, Chinese and Korean examination outcomes; Taiwan and Singapore filings exist but at far lower volume, and WIPO/PCT coverage is thin enough that regional strategies likely diverge by filer.
| Assignee | Recent year | YoY |
|---|---|---|
| Siliconware Precision Industries Co., Ltd. | 0 | -100% |
| International Business Machines Corporation (IBM) | 0 | — |
| Chipbond Technology Corporation | 0 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| Kepler Computing | 0 | — |
| Advanced Semiconductor Engineering (ASE Technology) | 0 | — |
| Agency for Science, Technology and Research (A*STAR) | 0 | — |
| VOLANTIS SEMICONDUCTOR INC | 0 | -100% |
Where to take this analysis
The filing and citation patterns above point to specific next checks before committing engineering or legal resource to this space.
Run a freedom-to-operate check against the most-cited records
The five most-cited records in this corpus, spanning fan-out molding, panel-based TSV substrates and interposer-mounted chip structures, are the prior art most likely to have generated dependent claims across later filers. Any new interposer or bridge design should be checked against these first.
Open Eureka to trace citation treesWatch for renewed filing from the momentum-zero assignees
Six major assignees show zero filings in the latest tracked year after prior activity. Given publication lag, some of that activity may already be in the pipeline and simply not yet published – worth a standing watch rather than a one-time check.
Set up assignee tracking in EurekaEvaluate the under-claimed sub-areas before drafting
Warpage-compensated stacking, fine-pitch microbump yield control and HBM-to-logic thermal bridge paths all sit at lower filing density than the core H01L/H10W cluster – a first-mover claim there faces less crowded prior art.
Explore white space with EurekaCommon questions on 2.5D interposer and silicon bridge patents
A 2.5D interposer is a substrate, typically silicon, placed between one or more dies and the package base to route fine-pitch signals and provide vertical electrical paths, usually through silicon vias, between stacked components such as logic and HBM memory. It sits alongside rather than inside the die stack, which distinguishes it from full 3D through-silicon-via die stacking. Patent claims in this space typically combine the interposer structure itself with a specific manufacturing step, such as via formation, microbump attachment or warpage control during assembly.
The tracked assignee ranking in this dataset includes established outsourced semiconductor assembly and test firms, foundries and IDMs, several of which show substantial historical filing but zero activity in the most recent tracked year. Given an 18-month typical publication lag, recent-year zero counts should be read cautiously rather than as a definitive market exit. A cross-check against each firm's public roadmap for HBM-integrated or fan-out products is the more reliable signal of continued investment.
Filings in this corpus rose from a 2022 low of 2 to a 2023 peak of 13, and the years since show lower or unreported counts. Part of that recent drop is a publication-lag artefact: filings made in 2025 or 2026 often are not published until 18 months later, so the true 2025-2026 filing rate is understated in any dataset pulled today. The remainder may reflect that core structural claims around the basic interposer-plus-TSV architecture were staked out earlier, pushing later filers toward narrower, more specific improvements rather than foundational filings.
US20110127662A1, assigned to STATS ChipPac Management, claims a packaging method that connects a silicon interposer carrying a through silicon via to a mounted device, then encapsulates the assembly with the interposer's external side left substantially exposed. It is a structural and process claim rather than a claim over the general concept of silicon interposers, so it constrains specific encapsulation-and-exposure sequences rather than the whole 2.5D packaging field. Any new design using a similar exposed-interposer encapsulation step should be checked against this filing's claim language directly rather than assumed to be blocked outright.
Based on IPC composition, the bulk of filing activity concentrates in core semiconductor device classes (H01L, H10W), while classes touching MEMS integration, AI-accelerator-specific routing and general printed circuit assembly carry far fewer records. Warpage-compensated stacking, fine-pitch microbump yield control and HBM-to-logic thermal bridge paths sit adjacent to the dense cluster but are not carrying the bulk of filing volume, making them worth a closer prior-art check before assuming the space is crowded. This pattern indicates claim density around basic interposer structure, not necessarily around the manufacturing controls that determine actual production yield.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.