2D Material Graphene Semiconductor 2026 — PatSnap Eureka
2D Material Graphene Semiconductor Application Landscape 2026
From graphene’s isolation in 2004 to wafer-scale CMOS integration today, this patent and literature landscape maps the key technical clusters, dominant assignees, and emerging directions shaping post-silicon electronics through 2025. TSMC holds 10+ active US patents; contact resistance remains the defining unsolved barrier.
Graphene and the 2D Semiconductor Family
The 2D graphene semiconductor technology field encompasses a family of atomically thin materials—led by graphene but increasingly complemented by transition metal dichalcogenides (TMDCs such as MoS₂, WS₂, MoSe₂, WSe₂), hexagonal boron nitride (h-BN), black phosphorus (phosphorene), MXenes, and monoelemental analogs (silicene, germanene, stanene)—applied to next-generation semiconductor device architectures. Publication dates in the retrieved dataset span from 2011 to 2025, with patent records covering 15 granted or pending patents from identified assignees.
The fundamental technical challenge is well-established: graphene’s zero-bandgap (semimetallic) nature limits direct use as a transistor channel material. This drives a dual-track innovation path: (1) bandgap engineering of graphene itself, and (2) the adoption of complementary 2D semiconductors with intrinsic bandgaps for active device layers, with graphene retained as a transparent conducting electrode, contact layer, or carrier transport layer. Research on 2D material analytics increasingly draws on patent landscaping tools to track these diverging pathways.
Computationally screened databases of more than 250 candidate 2D semiconductors and material families isoelectronic to phosphorene with more than 400 members have been identified in the literature, underscoring the breadth of the design space. External bodies such as ITU and IEEE have tracked 2D materials in next-generation communications standards contexts.
Three Phases of 2D Semiconductor Maturity
From foundational science through device demonstration to pre-commercial scaling, the dataset reveals a clear three-phase evolution spanning 2011 to 2025.
Four Patent Clusters Defining the 2D Semiconductor Landscape
The retrieved dataset organises into four primary innovation clusters, each reflecting a distinct engineering challenge and commercial trajectory.
2D Material FET Channel Engineering
The dominant patent cluster, driven primarily by TSMC and Samsung. Replaces silicon as the channel material in FETs with atomically thin 2D semiconductors (primarily TMDCs and phosphorene), exploiting superior electrostatic gate control at sub-10nm gate lengths, body thickness of ~0.7 nm, and competitive carrier mobility. Two primary gate geometries: lateral planar FETs and vertical FETs enabling ultra-compact device footprints. The 2022 literature benchmarks these against the 0.7 nm IRDS node for 2034. Key patents include TSMC’s integrated device series and Samsung’s polycrystalline 2D channel devices.
Sub-10nm gate control · 0.7 nm body thickness3D Nanosheet and Heterogeneous Integration
Emerging most strongly in 2023–2025 filings, this cluster targets 3D stacked transistor architectures where 2D material channels (typically MoS₂, WS₂, or similar TMDCs) are grown selectively around silicon or other semiconductor nanosheets using seed-layer-mediated deposition. Designed to maintain compatibility with existing CMOS manufacturing lines while extending scaling to sub-5nm nodes. Tokyo Electron Limited’s three US patents (2023–2025) are the primary signals, alongside TSMC’s doped 2D channel nanosheet patent (2022). This approach directly targets gate-all-around (GAA) architectures for sub-3nm nodes.
GAA sub-3nm · seed-layer deposition · Tokyo ElectronGraphene & 2D Optoelectronics
A large body of retrieved literature and several patents address optoelectronic applications. Graphene’s broadband optical absorption, high carrier mobility, and compatibility with photonic waveguides make it a candidate for telecommunications-speed photodetectors and optical modulators at 1310–1550 nm telecom wavelengths. TMDCs contribute direct bandgaps (visible to near-IR) enabling LEDs and solar cells. Van der Waals heterostructures combining different 2D materials are a particularly active design space, with a 2024 CN patent targeting PCSEL-on-silicon via van der Waals epitaxy. See also materials innovation analytics for photonic applications.
1310–1550 nm telecom · van der Waals heterostructuresHeterostructures and Van der Waals Assembly
Encompasses alloying, layer-number control, strain engineering, and van der Waals stacking to tailor the electronic bandgap of 2D materials. The literature identifies more than 400-member material families isoelectronic to phosphorene and computationally screened databases of more than 250 candidate 2D semiconductors. Ferroelectric phase reconstruction in wide-bandgap 2D films (Xidian University, CN, 2024) and graphene-on-Ga₂O₃ power electronics (Xi’an Ruixin, CN, 2024) represent novel directions targeting neuromorphic, memory-in-logic, and high-power applications. WIPO patent statistics confirm accelerating filings in this sub-domain.
Ferroelectric 2D · Ga₂O₃ platform · neuromorphicGeographic & Temporal Patent Distribution
Jurisdiction breakdown and filing phase activity from the 2D material graphene semiconductor dataset, 2013–2025.
Patent Jurisdiction Distribution
US dominates at approximately 80% of patents in this dataset; CN contributes 4 records (2 from 2024); EP and IN each contribute 2 records.
Patent Filing Activity by Phase (2011–2025)
Filing intensity increases sharply from Phase 2 onward; Phase 3 (2022–2025) contains the most recent TSMC, Tokyo Electron, and Chinese filings targeting sub-5nm nodes.
Where 2D Graphene Semiconductors Are Being Applied
Six distinct application domains emerge from the patent and literature dataset, each with a different maturity level and dominant assignee profile.
| Application Domain | Key Technology | Representative Assignees | Maturity Signal |
|---|---|---|---|
| Advanced Logic / CMOS Scaling | 2D FET channels for sub-5nm nodes; IRDS 2034 roadmap target at 0.7 nm node | TSMC (10+ US patents), Samsung Electronics | Most mature; active patent filings through 2025 |
| Telecommunications & Photonic Integration | Graphene optical modulators and photodetectors at 1310–1550 nm; PCSEL-on-silicon via van der Waals epitaxy | Individual inventor (CN, 2024); literature-dominated | Active; 2024 CN patent for silicon photonic monolithic chip |
| Infrared Sensing & Defense | Mid-infrared (MIR) optoelectronics; night vision, remote sensing, target acquisition | Literature-dominated (2022 reviews) | Research stage; no dominant patent assignee identified |
Five Strategic Signals for R&D and IP Teams
Based on the most recent filings and literature convergence in this dataset, five strategic implications emerge for organisations monitoring the 2D semiconductor space.
TSMC’s IP Dominance Is Broad and Deep
With more than 10 active or pending US patents covering lateral, vertical, and nanosheet 2D transistor architectures, TSMC has established strong freedom-to-operate barriers for any foundry or fabless company pursuing 2D channel FET manufacturing in the US. R&D teams must perform careful FTO analysis before committing to TSMC-adjacent process flows. PatSnap Analytics provides FTO workflow tools for exactly this scenario.
Contact Resistance Is the Defining Unsolved Problem
Multiple literature records and the 2025 TSMC LDD patent converge on source-drain contact resistance as the primary barrier between laboratory demonstration and manufacturable 2D FETs. IP positions covering low-resistance contact schemes—semimetal contacts, graphene electrodes on TMDCs, doped source-drain extensions—will be strategically critical. The PatSnap customer base includes semiconductor R&D teams tracking exactly this bottleneck.
China Accelerating in Distinct Application Verticals
Rather than competing directly with TSMC and Samsung on logic scaling, Chinese assignees in this dataset are targeting power electronics (Ga₂O₃+graphene), silicon photonics integration, and ferroelectric 2D materials—potentially establishing strong regional IP positions in sectors where US and Korean players have less coverage. CN contributes 4 patent records with 2 from 2024 alone. WIPO data corroborates accelerating Chinese semiconductor filings broadly.
Five Frontier Directions from the Most Recent Filings
Based on the most recent patents (2023–2025) retrieved in this dataset, five directions are most clearly signalled for the next phase of 2D semiconductor development.
3D Nanosheet + 2D Channel Co-integration
Tokyo Electron Limited’s 2023–2025 patents describe methods to selectively grow 2D material around semiconductor nanosheet bridges using seed layers, directly targeting gate-all-around (GAA) architectures for sub-3nm nodes. The 2025 filing on 3D selective material transformation to integrate 2D material elements is the most recent signal of this direction. PatSnap IP analytics tools can map competitive white space in this cluster.
GAA · sub-3nm · seed-layer growthSource-Drain Engineering in 2D FETs
TSMC’s 2D-Channel Transistor Structure with Source-Drain Engineering (filed 2025, US pending) introduces light-doped source/drain (LDD) features via ion implantation into 2D material layers, addressing the critical contact resistance bottleneck—currently one of the top challenges for practical 2D FET deployment. This is the most recent frontier patent in the dataset. NIST semiconductor metrology standards are relevant to LDD characterisation at this scale.
LDD · ion implantation · contact resistanceGraphene in Wide-Bandgap Power Electronics
The 2024 CN patent from Xi’an Ruixin Guangtong Information Technology Co., Ltd. combines graphene conducting channels with Ga₂O₃/(AlₓGa₁₋ₓ)₂O₃ heterojunction platforms, aiming to replace 2DEG channels in high-power HEMTs. This offers a potentially disruptive path for next-generation power switching in RF power amplifiers and power switching devices—a vertical where US and Korean players have less current IP coverage.
Ga₂O₃ HEMT · RF power · 2DEG replacementFerroelectric 2D Wide-Bandgap Materials
Xidian University’s 2024 CN patent on two-dimensional reconstructed ferroelectric-phase wide-bandgap semiconductor materials introduces polarization-modulated gating in ultrathin 2D channels, combining quantum confinement with non-volatile ferroelectric memory effects. This is a direction toward neuromorphic and memory-in-logic applications—a convergence point between 2D semiconductors and next-generation compute architectures. PatSnap materials solutions covers ferroelectric thin-film IP landscapes.
Ferroelectric gating · neuromorphic · memory-in-logic2D Material Graphene Semiconductor — key questions answered
Graphene’s zero-bandgap (semimetallic) nature limits its direct use as a transistor channel material. This drives a dual-track innovation path: bandgap engineering of graphene itself, and the adoption of complementary 2D semiconductors with intrinsic bandgaps for active device layers, with graphene retained as a transparent conducting electrode, contact layer, or carrier transport layer.
TSMC is by far the most prolific single assignee, with 10+ US patents identified covering 2D channel FETs, vertical transistors, nanosheet integration, and source-drain engineering. Samsung Electronics holds 4 patents across US and EP jurisdictions, and Tokyo Electron Limited holds 3 US patents targeting 3D nanosheet structures with 2D material channels.
Multiple literature records and the 2025 TSMC LDD patent converge on source-drain contact resistance as the primary barrier between laboratory demonstration and manufacturable 2D FETs. IP positions covering low-resistance contact schemes (semimetal contacts, graphene electrodes on TMDCs, doped source-drain extensions) will be strategically critical.
The main application domains identified in the dataset include: advanced logic and CMOS scaling (sub-5nm nodes), telecommunications and photonic integration (graphene optical modulators and photodetectors at 1310–1550 nm), infrared sensing and defense (mid-infrared optoelectronics), energy harvesting and storage (polymer solar cells, supercapacitors), biosensing and bioelectronics, and high-power and high-frequency electronics (Ga2O3+graphene HEMTs).
The most recent filings (2023–2025) signal five emerging directions: 3D nanosheet + 2D channel co-integration for sub-3nm GAA architectures; source-drain engineering in 2D FETs to address contact resistance; graphene in wide-bandgap power electronics on the Ga2O3 platform; ferroelectric 2D wide-bandgap materials for neuromorphic and memory-in-logic applications; and silicon photonic monolithic integration with 2D layers for PCSEL-on-silicon.
Rather than competing directly with TSMC and Samsung on logic scaling, Chinese assignees in this dataset are targeting power electronics (Ga2O3+graphene), silicon photonics integration, and ferroelectric 2D materials—potentially establishing strong regional IP positions in sectors where US and Korean players have less coverage. CN contributes 4 patent records including 2 from 2024.
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