3D NAND Flash Advanced Materials Patents: Leaders & Trends 2026
- Filing already peaked. 2018 recorded 6 filings, the high point of the series, with the midpoint year 2022 showing zero — the dataset reads flat-to-declining rather than growing.
- US filing dominates. 33 of the tracked records route through the United States receiving office versus 4 at the EPO and 3 via WIPO, concentrating enforcement risk in one jurisdiction.
- Citation weight sits with early vertical-cell claims. The most-cited record in the set, a 3D semicircular vertical NAND string design, carries 163 citations — more than double the next-ranked document.
What this landscape covers
This landscape tracks patent families at the intersection of 3D NAND / vertical NAND architecture and advanced memory materials — charge-trap nitride, channel polysilicon, ferroelectric memory material, and related deposition chemistry under C23C16. It is a narrow cut of a large field: 40 published records across roughly a decade of filing, concentrated in H10B memory-device manufacture and H01L semiconductor-device classifications.
Because publication lags filing by around 18 months, the most recent year in the trend chart is always undercounted and should not be read as a drop-off on its own. The dataset is small enough that individual patents — rather than broad statistical patterns — carry most of the signal here.
Filing trend and technology composition
Two views of the same 40 families: how filing activity moved year over year, and which IPC subclasses the claims actually sit in.
A short, front-loaded filing curve
Filing opened at 1 record in 2017, rose to a peak of 6 in 2018, and had fallen back to zero by the 2022 midpoint of the series. That shape is consistent with a technology area where the core architectural claims were staked out early and later activity shifted into adjacent or unclassified work not captured by this search string.
Concentrated in memory-device manufacture
All 40 records classify under H10B (memory device manufacture), and 37 also carry an H01L semiconductor-device code — the two are effectively co-occurring in this set. G11C (static and digital memories) appears in 18 records, marking a secondary cluster around read/write and array-control claims, while H10W, H10D and H10P each register only a handful of hits, suggesting those adjacent classifications are lightly worked by this filing population.
Shares are the percentage of the 40 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on 3D NAND Flash Advanced Materials with Eureka
This page is one run against one query. Ask Eureka your own question about 3d nand flash advanced materials and every answer comes back with the patent numbers behind it.
Try EurekaThe documents carrying the most citation weight
US9711229B1 — 3D NAND with partial block erase
Filed by Sandisk Technologies, the patent describes performing a partial-block erase on a subset of vertical NAND strings within a shared memory array. Strings connected to different drain-side select lines but sharing a common word line are selectively erased without disturbing the rest of the block, using the drain-side select-line grouping to isolate which strings participate in a given erase operation.Granted 2017-07-18 — one of the higher-cited records in this set at 59 citations.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20160071861A1 | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and met… | 163 |
| 2 | US20170125538A1 | Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines | 96 |
| 3 | US20160071860A1 | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and met… | 72 |
| 4 | US9711229B1 | 3D NAND with partial block erase | 59 |
| 5 | US20180233513A1 | Three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block | 53 |
| 6 | US20170125433A1 | 3D NAND device with five-folded memory stack structure configuration | 52 |
| 7 | US20160260732A1 | Vertical thin-channel memory | 51 |
| 8 | US9728546B2 | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and met… | 50 |
| 9 | US20160099254A1 | Memory Hole Structure in Three Dimensional Memory | 44 |
| 10 | US10043819B1 | Method for manufacturing 3D NAND memory using gate replacement, and resulting structures | 42 |
Citation counts are drawn from the searched corpus only and skew toward older filings; treat them as a measure of influence within this dataset, not as a ranking of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three read-outs from the trend, the classification split and the citation table, translated into what they imply for someone deciding where to file next.
The architectural land-grab already happened
The peak year, 2018, is now several years behind the most recent complete data point. A flat-to-declining curve on a narrow search string like this one usually means the foundational vertical-cell and charge-trap claims were filed early, and that later work has migrated into adjacent classifications this search does not capture — not that the underlying technology stopped moving.
Enforcement exposure is overwhelmingly US-based
With 33 of 40 records routed through the United States and only single-digit counts at the EPO and WIPO, freedom-to-operate work outside the US on this claim set is comparatively lightly tested. That does not mean the claims are weak elsewhere — it means fewer parties have chosen to contest them there.
Influence sits with two early vertical-cell families
The top-cited record — a 3D semicircular vertical NAND string with self-aligned floating-gate or charge-trap cell — is cited 163 times, well ahead of the second-ranked document at 96. Design-around analysis should start with these two before moving down the table.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to 3d nand flash advanced materials, with the prior art for and against each one.
Who is active, and where the claim space is still open
Recent-year filing momentum across the named assignees in this set is uniformly flat: every tracked assignee shows zero filings in the latest year, including a -100% year-on-year change for one entity. That is consistent with the overall trend line and should be read as a small, mature dataset rather than an active race.
No assignee shows recent-year filing growth
The recent-year momentum table shows every tracked assignee — spanning US and Asian semiconductor memory makers and equipment suppliers — at zero filings in the most recent year, with one entity recording a full year-on-year drop. This is a lagging-indicator caveat as much as a finding: publication delay means very recent filings may simply not have surfaced yet.
Early filers still anchor the citation graph
The most-cited documents in this set date to the earlier part of the filing window and describe core vertical-cell geometries and word-line nucleation-layer chemistry. New entrants should expect any charge-trap or channel-polysilicon claim to be read against this earlier art first.
US-first filing strategy is the norm here
The receiving-office split shows a clear US-first pattern, with EPO and PCT routes used far less often. Competitors weighing entry into Europe or seeking broader PCT coverage face a thinner prior-art wall in those offices than in the US.
| Assignee | Recent year | YoY |
|---|---|---|
| SanDisk Technologies LLC | 0 | — |
| Macronix International Co., Ltd. | 0 | — |
| Intel Corporation | 0 | — |
| Intel NDTM US LLC | 0 | -100% |
| Tokyo Electron Limited | 0 | — |
Where to take this analysis
This page surfaces the pattern; the next steps depend on whether you are clearing a design or scouting a gap.
Run a design-around check against the top-cited claims
Start with the 163- and 96-citation records before drafting any charge-trap nitride or vertical-string claim — they anchor the citation graph in this dataset and are the most likely first-cited art in an examination.
Analyze these claims in EurekaMap the under-claimed branches to your own roadmap
Ferroelectric memory material integration and channel polysilicon grain-boundary control show thin filing density relative to the core vertical-cell claims — worth a closer look if your roadmap touches either.
Explore white space in EurekaCommon questions on 3D NAND advanced materials patents
In this landscape it means claims built around charge-trap nitride layers, channel polysilicon, ferroelectric memory materials, or the deposition chemistry (grouped under IPC C23C16) used to form them inside a vertical NAND stack. These are distinct from pure architectural claims about string geometry or select-line wiring, though in practice the two overlap heavily — 37 of the 40 records in this set carry both an H10B memory-manufacture code and an H01L semiconductor-device code. A practitioner searching this space should expect material-composition claims to be entangled with structural claims rather than filed separately.
The dataset shows filing rising to 6 records in 2018 and falling to zero by the 2022 midpoint, which typically indicates that the foundational architectural and material claims for this specific search string were staked out early in the vertical NAND transition. It does not necessarily mean the underlying technology went quiet — later work may have shifted into adjacent classifications not captured by this particular IPC and keyword combination. Publication lag of roughly 18 months also means the final one or two years of any patent trend are always undercounted, so treat the most recent years with caution.
The most-cited record in this set is a 3D semicircular vertical NAND string patent describing self-aligned floating-gate or charge-trap cell memory cells, with 163 citations — more than double the next-ranked document at 96. High citation counts inside a searched corpus tend to favour older filings simply because they have had more time to be cited, so this should be read as a signal of foundational influence on later filings rather than a claim that the patent is still the most commercially relevant today. Anyone drafting new claims in this area should still expect examiners to cite it as prior art.
The recent-year momentum data shows every tracked assignee at zero filings in the latest year, including one with a full year-on-year decline, but this needs to be read alongside the publication lag caveat. Patents filed in the last 12-18 months often have not yet published, so a zero in the most recent year is expected even for an assignee that is still actively filing. The more reliable read is the multi-year trend line, which does show the field's peak filing activity behind it rather than ahead.
Based on the IPC composition, branches like H10W and H10D register only a handful of hits compared to the 40-record core in H10B, and specific sub-areas such as ferroelectric memory material integration, channel polysilicon grain-boundary control, and word-line nucleation-layer chemistry show comparatively light filing density. That does not guarantee an unopposed path — a proper freedom-to-operate search is still required — but it does suggest these branches are less densely claimed than the core vertical-cell and charge-trap geometry that the top-cited patents cover.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.