The core classification is H10B, which covers memory device manufacture and captures essentially all of the structural and process claims around 3D NAND stacking, staircase contacts and bonding. Related claims also appear under H01L for general semiconductor device structure, and under process-specific classes like B24B (grinding and polishing) and C09G (polishing compositions) when the claim covers a fabrication step rather than the device itself. Searching H10B alone will miss claims that are framed as a polishing or bonding process rather than a device structure, so both angles are worth checking.

This dataset shows a peak of 11 published records in 2023 after a flat period with effectively zero filings at the 2022 midpoint. A single-year spike like this usually corresponds to a specific product generation or process node reaching a filing deadline, rather than a sustained increase in R&D investment. Because publication lags actual filing by roughly 18 months, the apparent drop-off after 2023 should be checked against priority dates before concluding that filing activity has genuinely slowed.

CMOS-under-array is an integration approach where the control logic circuitry is built underneath the memory cell array rather than beside it, which saves die area as NAND stacks grow taller. It appears in this search because it is one of the named system-integration techniques used to keep 3D NAND scaling economical as layer counts increase. Claims in this space tend to focus on thermal budget management and interconnect routing between the logic layer and the array above it, both of which show limited coverage in this particular dataset.

The representative filing in this dataset, US20250107081A1 from Macronix International, claims a specific staircase contact structure that uses a dedicated stop layer to prevent contacts from punching through into the interconnect below. This is a narrow structural fix rather than a broad staircase-architecture claim, so it blocks that specific etch-stop arrangement without covering staircase contacts generally. Because the whole corpus sits inside one IPC subclass with limited assignee diversity, a full claim chart across the 16 families is needed to see which staircase approaches remain open.

Based on the IPC spread in this corpus, wafer-bonding alignment tolerance and post-bond polishing chemistry are only lightly claimed compared with the core staircase and stacking structures. That does not mean the space is empty — it means this particular search, limited to string stacking, wafer bonding, CMOS-under-array and system integration terms, surfaces few claims there. A team considering filing in bonding alignment or polishing composition chemistry should run a dedicated search on those terms alone before assuming the space is open, since a narrow search like this one can understate coverage that exists under different classification.