The most heavily cited records in this dataset, several exceeding 250-400 citations, describe the foundational vertical NAND stack and charge-trap architecture and date to the early 2010s. Current major assignees active in the space include Samsung, SanDisk, Yangtze Memory Technologies, Intel, Macronix and Applied Materials, based on the ranking of 378 tracked patent families. Note that the companies holding the oldest, most-cited foundational patents are not necessarily the same ones filing most actively today, since citation counts favour older records simply by virtue of having had more time to accumulate references.

No — filings rose from 17 in 2017 to a peak of 63 in 2020, then declined to 19 by the 2022 midpoint, indicating the technology's core structural claims are largely staked out rather than still expanding. The most recent one to two years in any such trend should be read cautiously, since publication typically lags actual filing by around 18 months and will understate true recent activity. Even accounting for that lag, the multi-year decline from the 2020 peak suggests a genuine slowdown rather than a data artefact alone.

This landscape is scoped to claims involving channel hole etch, word-line stack construction, charge trap layer design, string stacking and vertical channel formation, corresponding to IPC classes H10B41/27, H10B43/27 and G11C16. The data shows manufacturing and structural claims (H10B, 302 of 378 families) substantially outweigh circuit-level claims (G11C, 131), meaning most of the competitive claim activity is about how the vertical stack is physically fabricated rather than how the memory circuit operates. Adjacent classes like C23C (coating and deposition) and G06F (data processing) appear only marginally, marking the edges of the field rather than active centres of filing.

Based on the IPC composition and recent representative filings, narrower structural variants such as piezoelectric gate layer integration, air-gap isolation within the memory stack, and specific thin-film deposition methods for charge trap layers show thinner coverage relative to the dense core claims on channel hole etch and word-line stacking. A recent IMEC filing (US20250212412A1) illustrates one such variant, combining a standard charge-trap stack with a piezoelectric gate layer separated by an air gap. These edges are worth checking specifically because the core vertical-stack claim space, per the 2020 filing peak, is already heavily occupied.

This pattern — appearing across Yangtze Memory Technologies, Samsung, SanDisk, Intel, Macronix and Applied Materials alike — is a direct effect of patent publication lag, which typically runs about 18 months from filing to public disclosure. A zero in the latest tracked year does not mean these companies stopped filing; it means those filings have not yet published. The more meaningful signal is the multi-year decline from the 2020 peak through the 2022 midpoint, which predates the lag window and points to an actual slowdown in new structural claims.