3D NAND Flash Patents: Who Leads, Where the Gaps Are 2026
- Filing has cooled since its 2017 peak. 31 families that year against a 2022 midpoint of 23 and a near-empty final year — claim activity is settling rather than accelerating.
- G11C dominates the classification mix. 293 of 351 families sit in static and digital memory (G11C), far ahead of processing (G06F) and device manufacture (H10B), showing where examiners will look first.
- The United States absorbs the bulk of filings. 206 records route through the USPTO versus 35 at the EPO and 30 in China — a US-first filing pattern that shapes where freedom-to-operate risk concentrates.
What the 3D NAND patent record actually shows
3D NAND moved from planar scaling limits to vertical layer stacking, and the patent record follows that shift: claims cluster around channel hole etch, cell-to-cell interference, wear leveling and read disturb mitigation rather than raw density alone. The search set spans 2015 through the 2026 cut-off and returns 351 patent families once continuations and multi-jurisdiction duplicates are collapsed to a single family count. Filing activity peaked in 2017 and has not returned to that level since, which is consistent with a technology where the core architecture is settled and remaining claims are increasingly about reliability and manufacturing tolerance rather than new cell geometry.
Because publication lags filing by roughly eighteen months, the most recent year in the trend understates real activity — a thin final year is expected, not necessarily a sign the field has gone quiet. Treat the 2017 peak and the 2022 midpoint as the more reliable markers of where filing behaviour actually sits.
Let an AI agent run this analysis on your own technology
Pick a task. Every answer cites the patents behind it.
Filing trend and technology composition
Two views of the same 351 families: how filing volume has moved year over year, and how those filings split across IPC subclasses.
A peak in 2017, a flat-to-declining decade after
31 families filed in 2017 is the high point in the window. By 2022, the midpoint year, volume had settled to 23, and the trajectory into the most recent (partial) year continues downward. This is not a young, fast-growing field on this evidence — it reads as a maturing one where the architecture is fixed and the remaining filing activity is concentrated on refinement.
G11C carries the weight; manufacturing and processing trail
G11C (static and digital memories) appears in 293 of 351 records, well ahead of G06F (electric digital data processing, 91), H01L (semiconductor devices, 90) and H10B (memory device manufacture, 88). The gap between G11C and everything else suggests most claim drafting is happening at the memory-operation level — addressing, error handling, wear management — rather than at the physical device or fabrication level, even though channel hole etch and layer stacking are named search terms.
Shares are the percentage of the 351 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on 3D NAND Flash Technology with Eureka
This page is one run against one query. Ask Eureka your own question about 3d nand flash technology and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this corpus
US20180068726A1 — Error mitigation for 3D NAND flash memory
NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error conFiled by Sandisk Technologies, Inc. — abstract truncated as published.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US8437189B1 | Method and apparatus for storing data in a NAND flash memory | 508 |
| 2 | US20090037652A1 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules | 270 |
| 3 | US20160141299A1 | Vertical and 3D memory devices and methods of manufacturing the same | 217 |
| 4 | US7177977B2 | Operating non-volatile memory without read disturb limitations | 210 |
| 5 | US6175522B1 | Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory device | 197 |
| 6 | US9400749B1 | Host interleaved erase operations for flash memory controller | 184 |
| 7 | US7710777B1 | Semi-volatile NAND flash memory | 178 |
| 8 | US9727454B2 | Memory controller that provides addresses to host for memory location matching state tracked by memory contro… | 108 |
| 9 | US6380033B1 | Process to improve read disturb for NAND flash memory devices | 100 |
| 10 | US9652376B2 | Cooperative flash memory control | 99 |
Citation counts reward older filings simply because they have had longer to accumulate citations inside this corpus — read them as markers of influence on later drafting, not as a ranking of current technical relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the numbers mean for a filing decision
Three patterns stand out once the raw counts are read against each other.
The peak is behind the field, not ahead of it
2017's 31 families is the high-water mark; the 2022 midpoint of 23 and the drop-off into the final year both point the same direction. New entrants filing broad architecture claims now compete against a decade of prior art on layer stacking and channel hole etch specifically.
Memory-operation claims dominate over device claims
G11C's lead over H01L and H10B means the densest prior art sits in addressing, error handling and array-operation claims — the layer where read disturb and wear leveling filings actually live — rather than in etch or stacking hardware itself.
Freedom-to-operate risk is US-weighted
With 206 of 351 records routed through the USPTO against much smaller EPO, China, South Korea and Taiwan counts, clearance work for a 3D NAND product line should start with a US-first search before assuming European or Chinese exposure is comparable.
Old foundational filings still anchor the field
The most-cited records date back to earlier NAND operating and storage methods rather than to the 3D-specific filings; that is expected of a citation count inside a fixed corpus, and it should not be read as those older patents remaining the most commercially active today.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to 3d nand flash technology, with the prior art for and against each one.
Who is filing, and how much room is left
Recent-year momentum across the named assignees is flat to negative across the board, which is itself informative: no single company is currently pulling away with a new filing surge.
No assignee is accelerating right now
Every tracked assignee shows zero or negative year-over-year movement in the latest year, including a 100% drop for at least one major filer. That flat picture across the board is consistent with a technology in a refinement phase rather than an active land-grab.
Co-filing is thin and mostly single-inventor linked
Only ten co-assignee pairs appear in the dataset, and the strongest is a count of three. Most 3D NAND filings in this set are filed by a single corporate assignee rather than through joint ventures or cross-licensed development programmes.
Filing strategy still centres on the US and PCT route
The receiving-office split — US, EPO, WIPO, China, South Korea, Taiwan — shows a conventional global-filing ladder led by the US, with WIPO/PCT filings (32) used as the bridge into secondary markets rather than direct-to-China or direct-to-Korea strategies dominating.
| Assignee | Recent year | YoY |
|---|---|---|
| Yangtze Memory Technologies Co., Ltd. | 1 | 0% |
| SanDisk Technologies LLC | 0 | — |
| Intel Corporation | 0 | — |
| Micron Technology, Inc. | 0 | -100% |
| Macronix International Co., Ltd. | 0 | — |
| SK hynix Inc. | 0 | — |
| SanDisk Corporation | 0 | — |
| Western Digital Israel Ltd. | 0 | — |
Where to take this next
The dataset points to specific follow-up work depending on whether the goal is clearance, drafting or monitoring.
Run a freedom-to-operate check on read disturb and wear leveling claims
Given G11C's concentration and the US filing weighting, a targeted FTO search on the memory-operation layer — rather than a broad 3D NAND search — will surface the claims most likely to matter for a new product.
Start a claim searchDraft around the under-claimed manufacturing branches
Channel hole etch profile control and multi-tier stacking alignment show up in the search terms but with thinner density than operation-layer claims — a first-filer position there is still available.
Explore white spaceWatch for the next filing cycle before it publishes
Because publication lags filing by around eighteen months, the flat recent-year numbers may already be masking a new cycle of filings not yet visible in this cut. Set a monitor rather than concluding the field is closed.
Set up monitoringCommon questions about 3D NAND patents
This dataset identifies 351 patent families across the 2015–2026 window using a search built around 3D NAND, vertical NAND and NAND flash memory terms combined with layer stacking, channel hole etch, cell-to-cell interference, wear leveling and read disturb claim language. Using families rather than raw document counts avoids double-counting continuations and multiple jurisdictional filings of the same invention. The true figure for the technology as a whole will be larger since no single search string captures every adjacent claim, but 351 is a representative core set for the specific reliability and manufacturing themes this search targets.
The named assignees in the recent-year momentum data include major memory manufacturers such as SanDisk, Yangtze Memory Technologies, Intel, Micron, Macronix and SK hynix, each showing flat or declining year-over-year filing in the latest tracked year. No single company shows active growth in the most recent period, which suggests the leadership positions were established earlier in the filing history rather than through a current surge. Checking each assignee's full family count and filing history, not just recent momentum, is necessary before drawing conclusions about who holds the strongest current position.
Filing peaked at 31 families in 2017 and had fallen to 23 by the 2022 midpoint, with a further decline into the most recent partial year. This pattern is typical of a technology that has moved past its initial architecture-defining phase into a refinement phase, where the basic vertical-stacking approach is settled and remaining innovation concentrates on reliability techniques like wear leveling and read disturb mitigation rather than new cell geometry. It is also worth remembering that publication lags filing by around eighteen months, so the final year or two in any trend chart will always look thinner than it eventually turns out to be.
US20180068726A1, assigned to SanDisk Technologies, Inc., covers error mitigation for 3D NAND: detecting whether a page error is a read disturbance or a retention error, then triggering a refresh operation that rewrites data from an affected first page to a second page when the error is read-disturb related. That is a fairly specific remediation mechanism, not a claim over 3D NAND architecture generally, so it constrains designs that use this particular detect-then-refresh sequence rather than blocking read disturb mitigation as a category. Anyone building a competing error-mitigation scheme should compare their trigger condition and remediation action against this claim language specifically rather than assuming the entire read-disturb space is closed.
The classification data shows G11C (memory operation and addressing) heavily outweighing H01L, H10B and H10W, which points to thinner claim density in the device-manufacturing and physical-structure layers — specifically channel hole etch profile control and multi-tier layer stacking alignment. Co-assignee filing is also thin, with only ten pairs identified and the strongest pair at just three shared filings, suggesting collaborative or cross-licensed filing strategies are underused relative to solo corporate filing. Both observations point toward manufacturing-process claims and joint-development filing structures as areas with more room than the crowded memory-operation layer.
Research 3D NAND Flash Technology in depth with Eureka
Go past this page: query the whole 3d nand flash technology corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.